James Hogan cb539fd241 target-mips: Don't stop on [d]mtc0 DESAVE/KScratch ... Writing to the MIPS DESAVE register (and now the KScratch registers) will stop translation, supposedly due to risk of execution mode switches. However these registers are basically RW scratch registers with no side effects so there is no risk of them triggering execution mode changes. Drop the bstate = BS_STOP for these registers for both mtc0 and dmtc0. Fixes: 7a387fffce ("Add MIPS32R2 instructions, and generally straighten out the instruction decoding. This is also the first percent towards MIPS64 support.") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>		2017-08-02 17:01:27 +01:00
..
cpu-qom.h
cpu.c	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
cpu.h	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
dsp_helper.c
gdbstub.c
helper.c	target/mips: Implement segmentation control	2017-07-20 22:42:26 +01:00
helper.h	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
kvm_mips.h
kvm.c	vcpu_dirty: share the same field in CPUState for all accelerators	2017-07-04 14:30:03 +02:00
lmi_helper.c
machine.c	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
Makefile.objs
mips-defs.h
mips-semi.c
msa_helper.c
op_helper.c	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
TODO
trace-events	docs: fix broken paths to docs/devel/tracing.txt	2017-07-31 13:12:53 +03:00
translate_init.c	target/mips: Enable CP0_EBase.WG on MIPS64 CPUs	2017-07-21 03:23:44 +01:00
translate.c	target-mips: Don't stop on [d]mtc0 DESAVE/KScratch	2017-08-02 17:01:27 +01:00