Peter Xu cb135f59b8 q35: ioapic: add support for emulated IOAPIC IR ... This patch translates all IOAPIC interrupts into MSI ones. One pseudo ioapic address space is added to transfer the MSI message. By default, it will be system memory address space. When IR is enabled, it will be IOMMU address space. Currently, only emulated IOAPIC is supported. Idea suggested by Jan Kiszka and Rita Sinha in the following patch: https://lists.gnu.org/archive/html/qemu-devel/2016-03/msg01933.html Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2016-07-21 20:43:49 +03:00
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apic_internal.h	Clean up decorations and whitespace around header guards	2016-07-12 16:20:46 +02:00
apic-msidef.h	q35: ioapic: add support for emulated IOAPIC IR	2016-07-21 20:43:49 +03:00
apic.h	apic: move target-dependent definitions to cpu.h	2016-05-19 16:42:28 +02:00
ich9.h	ich9: implement SCI_IRQ_SEL register	2016-06-29 14:03:48 +02:00
intel_iommu.h	intel_iommu: Add support for PCI MSI remap	2016-07-20 19:31:04 +03:00
ioapic_internal.h	q35: ioapic: add support for emulated IOAPIC IR	2016-07-21 20:43:49 +03:00
ioapic.h	Clean up decorations and whitespace around header guards	2016-07-12 16:20:46 +02:00
pc.h	q35: ioapic: add support for emulated IOAPIC IR	2016-07-21 20:43:49 +03:00
topology.h	include: Clean up includes	2016-02-23 12:43:05 +00:00
x86-iommu.h	x86-iommu: introduce "intremap" property	2016-07-20 19:30:27 +03:00