qemu/target
Miodrag Dinic cab4888136 target/mips: fix msa copy_[s|u]_df rd = 0 corner case
This patch fixes the msa copy_[s|u]_df instruction emulation when
the destination register rd is zero. Without this patch the zero
register would get clobbered, which should never happen because it
is supposed to be hardwired to 0.

Fix this corner case by explicitly checking rd = 0 and effectively
making these instructions emulation no-op in that case.

Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-11 15:06:34 +01:00
..
alpha target/alpha: Use tcg_gen_lookup_and_goto_ptr 2017-06-19 11:11:25 -07:00
arm target/arm: Exit after clearing aarch64 interrupt mask 2017-06-19 11:11:26 -07:00
cris qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
hppa target/hppa: Use tcg_gen_lookup_and_goto_ptr 2017-06-05 09:25:42 -07:00
i386 target/i386: add the CONFIG_TCG into Makefiles 2017-07-05 09:12:44 +02:00
lm32 qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
m68k target/m68k: add fmovem 2017-06-29 20:29:57 +02:00
microblaze target-microblaze: Add CPU version 10.0 2017-07-04 09:22:20 +02:00
mips target/mips: fix msa copy_[s|u]_df rd = 0 corner case 2017-07-11 15:06:34 +01:00
moxie qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
nios2 target/nios2: Fix 64-bit ilp32 compilation 2017-06-05 09:25:42 -07:00
openrisc target/openrisc: Support non-busy idle state using PMR SPR 2017-05-04 09:39:14 +09:00
ppc target/ppc: Proper cleanup when ppc_cpu_realizefn fails 2017-06-30 14:03:31 +10:00
s390x virtio-scsi-ccw: use ioeventfd even when KVM is disabled 2017-07-05 19:45:02 +02:00
sh4 target/sh4: fix RTE instruction delay slot 2017-05-30 21:00:56 +02:00
sparc shutdown: Add source information to SHUTDOWN and RESET 2017-05-23 13:28:17 +02:00
tilegx migration: Remove unneeded includes of migration/vmstate.h 2017-06-01 18:49:22 +02:00
tricore qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
unicore32 cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
xtensa target/xtensa: handle unknown registers in gdbstub 2017-06-06 02:40:48 -07:00