ca5bed07d0
LQ has a constraint that RTp != RA, else SIGILL.
Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
new register pair, so that it cannot overlap the input address.
This requires new support in process_op_defs and tcg_reg_alloc_op.
Cc: qemu-stable@nongnu.org
Fixes: 526cd4ec01 ("tcg/ppc: Support 128-bit load/store")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
42 lines
899 B
C
42 lines
899 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define PowerPC target-specific constraint sets.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
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* Each operand should be a sequence of constraint letters as defined by
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* tcg-target-con-str.h; the constraint combination is inclusive or.
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*/
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C_O0_I1(r)
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C_O0_I2(r, r)
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C_O0_I2(r, ri)
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C_O0_I2(v, r)
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C_O0_I3(r, r, r)
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C_O0_I3(o, m, r)
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C_O0_I4(r, r, ri, ri)
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C_O0_I4(r, r, r, r)
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C_O1_I1(r, r)
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C_O1_I1(v, r)
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C_O1_I1(v, v)
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C_O1_I1(v, vr)
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C_O1_I2(r, 0, rZ)
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C_O1_I2(r, rI, ri)
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C_O1_I2(r, rI, rT)
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C_O1_I2(r, r, r)
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C_O1_I2(r, r, ri)
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C_O1_I2(r, r, rI)
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C_O1_I2(r, r, rT)
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C_O1_I2(r, r, rU)
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C_O1_I2(r, r, rZW)
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C_O1_I2(v, v, v)
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C_O1_I3(v, v, v, v)
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C_O1_I4(r, r, ri, rZ, rZ)
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C_O1_I4(r, r, r, ri, ri)
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C_O2_I1(r, r, r)
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C_N1O1_I1(o, m, r)
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C_O2_I2(r, r, r, r)
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C_O2_I4(r, r, rI, rZM, r, r)
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C_O2_I4(r, r, r, r, rI, rZM)
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