Jamin Lin 0559e60669 aspeed/smc: support different memory region ops for SMC flash region ... It set "aspeed_smc_flash_ops" struct which containing read and write callbacks to be used when I/O is performed on the SMC flash region. And it set the valid max_access_size 4 by default for all ASPEED SMC models. However, the valid max_access_size 4 only support 32 bits CPUs. To support all ASPEED SMC model, introduce a new "const MemoryRegionOps *" attribute in AspeedSMCClass and use it in aspeed_smc_flash_realize function. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>		2024-06-16 21:08:54 +02:00
..
aspeed_smc.h	aspeed/smc: support different memory region ops for SMC flash region	2024-06-16 21:08:54 +02:00
bcm2835_spi.h	hw/ssi: Implement BCM2835 SPI Controller	2024-02-02 13:51:59 +00:00
ibex_spi_host.h	Do not include hw/hw.h if it is not necessary	2023-02-27 09:15:38 +01:00
imx_spi.h	hw/ssi: imx_spi: Use a macro for number of chip selects supported	2021-02-02 17:00:54 +00:00
mss-spi.h
npcm7xx_fiu.h
npcm_pspi.h	hw/ssi: Add Nuvoton PSPI Module	2023-02-16 16:00:48 +00:00
pl022.h	arm: Update infocenter.arm.com URLs	2021-02-11 11:50:14 +00:00
sifive_spi.h	include: Include headers where needed	2023-01-08 01:54:22 -05:00
ssi.h	hw/ssi: Introduce a ssi_get_cs() helper	2023-09-01 11:40:04 +02:00
stm32f2xx_spi.h
xilinx_spips.h	hw/ssi/xilinx_spips: fix an out of bound access	2023-11-27 15:38:43 +00:00
xlnx-versal-ospi.h	hw/misc, hw/ssi: Fix some URLs for AMD / Xilinx models	2023-11-27 15:38:43 +00:00