c79aa350ea
NPCM7XX models have been commited after the conversion from
commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
Manually convert them.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
284 lines
7.4 KiB
C
284 lines
7.4 KiB
C
/*
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* Nuvoton NPCM7xx EMC Module
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_EMC_H
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#define NPCM7XX_EMC_H
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "net/net.h"
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/* 32-bit register indices. */
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enum NPCM7xxPWMRegister {
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/* Control registers. */
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REG_CAMCMR,
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REG_CAMEN,
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/* There are 16 CAMn[ML] registers. */
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REG_CAMM_BASE,
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REG_CAML_BASE,
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REG_CAMML_LAST = 0x21,
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REG_TXDLSA = 0x22,
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REG_RXDLSA,
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REG_MCMDR,
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REG_MIID,
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REG_MIIDA,
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REG_FFTCR,
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REG_TSDR,
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REG_RSDR,
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REG_DMARFC,
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REG_MIEN,
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/* Status registers. */
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REG_MISTA,
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REG_MGSTA,
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REG_MPCNT,
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REG_MRPC,
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REG_MRPCC,
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REG_MREPC,
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REG_DMARFS,
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REG_CTXDSA,
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REG_CTXBSA,
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REG_CRXDSA,
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REG_CRXBSA,
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NPCM7XX_NUM_EMC_REGS,
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};
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/* REG_CAMCMR fields */
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/* Enable CAM Compare */
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#define REG_CAMCMR_ECMP (1 << 4)
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/* Complement CAM Compare */
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#define REG_CAMCMR_CCAM (1 << 3)
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/* Accept Broadcast Packet */
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#define REG_CAMCMR_ABP (1 << 2)
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/* Accept Multicast Packet */
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#define REG_CAMCMR_AMP (1 << 1)
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/* Accept Unicast Packet */
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#define REG_CAMCMR_AUP (1 << 0)
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/* REG_MCMDR fields */
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/* Software Reset */
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#define REG_MCMDR_SWR (1 << 24)
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/* Internal Loopback Select */
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#define REG_MCMDR_LBK (1 << 21)
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/* Operation Mode Select */
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#define REG_MCMDR_OPMOD (1 << 20)
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/* Enable MDC Clock Generation */
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#define REG_MCMDR_ENMDC (1 << 19)
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/* Full-Duplex Mode Select */
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#define REG_MCMDR_FDUP (1 << 18)
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/* Enable SQE Checking */
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#define REG_MCMDR_ENSEQ (1 << 17)
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/* Send PAUSE Frame */
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#define REG_MCMDR_SDPZ (1 << 16)
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/* No Defer */
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#define REG_MCMDR_NDEF (1 << 9)
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/* Frame Transmission On */
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#define REG_MCMDR_TXON (1 << 8)
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/* Strip CRC Checksum */
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#define REG_MCMDR_SPCRC (1 << 5)
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/* Accept CRC Error Packet */
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#define REG_MCMDR_AEP (1 << 4)
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/* Accept Control Packet */
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#define REG_MCMDR_ACP (1 << 3)
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/* Accept Runt Packet */
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#define REG_MCMDR_ARP (1 << 2)
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/* Accept Long Packet */
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#define REG_MCMDR_ALP (1 << 1)
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/* Frame Reception On */
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#define REG_MCMDR_RXON (1 << 0)
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/* REG_MIEN fields */
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/* Enable Transmit Descriptor Unavailable Interrupt */
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#define REG_MIEN_ENTDU (1 << 23)
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/* Enable Transmit Completion Interrupt */
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#define REG_MIEN_ENTXCP (1 << 18)
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/* Enable Transmit Interrupt */
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#define REG_MIEN_ENTXINTR (1 << 16)
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/* Enable Receive Descriptor Unavailable Interrupt */
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#define REG_MIEN_ENRDU (1 << 10)
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/* Enable Receive Good Interrupt */
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#define REG_MIEN_ENRXGD (1 << 4)
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/* Enable Receive Interrupt */
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#define REG_MIEN_ENRXINTR (1 << 0)
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/* REG_MISTA fields */
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/* TODO: Add error fields and support simulated errors? */
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/* Transmit Bus Error Interrupt */
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#define REG_MISTA_TXBERR (1 << 24)
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/* Transmit Descriptor Unavailable Interrupt */
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#define REG_MISTA_TDU (1 << 23)
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/* Transmit Completion Interrupt */
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#define REG_MISTA_TXCP (1 << 18)
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/* Transmit Interrupt */
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#define REG_MISTA_TXINTR (1 << 16)
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/* Receive Bus Error Interrupt */
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#define REG_MISTA_RXBERR (1 << 11)
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/* Receive Descriptor Unavailable Interrupt */
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#define REG_MISTA_RDU (1 << 10)
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/* DMA Early Notification Interrupt */
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#define REG_MISTA_DENI (1 << 9)
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/* Maximum Frame Length Interrupt */
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#define REG_MISTA_DFOI (1 << 8)
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/* Receive Good Interrupt */
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#define REG_MISTA_RXGD (1 << 4)
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/* Packet Too Long Interrupt */
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#define REG_MISTA_PTLE (1 << 3)
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/* Receive Interrupt */
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#define REG_MISTA_RXINTR (1 << 0)
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/* REG_MGSTA fields */
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/* Transmission Halted */
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#define REG_MGSTA_TXHA (1 << 11)
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/* Receive Halted */
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#define REG_MGSTA_RXHA (1 << 11)
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/* REG_DMARFC fields */
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/* Maximum Receive Frame Length */
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#define REG_DMARFC_RXMS(word) extract32((word), 0, 16)
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/* REG MIIDA fields */
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/* Busy Bit */
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#define REG_MIIDA_BUSY (1 << 17)
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/* Transmit and receive descriptors */
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typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc;
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typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc;
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struct NPCM7xxEMCTxDesc {
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uint32_t flags;
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uint32_t txbsa;
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uint32_t status_and_length;
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uint32_t ntxdsa;
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};
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struct NPCM7xxEMCRxDesc {
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uint32_t status_and_length;
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uint32_t rxbsa;
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uint32_t reserved;
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uint32_t nrxdsa;
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};
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/* NPCM7xxEMCTxDesc.flags values */
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/* Owner: 0 = cpu, 1 = emc */
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#define TX_DESC_FLAG_OWNER_MASK (1 << 31)
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/* Transmit interrupt enable */
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#define TX_DESC_FLAG_INTEN (1 << 2)
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/* CRC append */
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#define TX_DESC_FLAG_CRCAPP (1 << 1)
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/* Padding enable */
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#define TX_DESC_FLAG_PADEN (1 << 0)
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/* NPCM7xxEMCTxDesc.status_and_length values */
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/* Collision count */
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#define TX_DESC_STATUS_CCNT_SHIFT 28
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#define TX_DESC_STATUS_CCNT_BITSIZE 4
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/* SQE error */
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#define TX_DESC_STATUS_SQE (1 << 26)
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/* Transmission paused */
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#define TX_DESC_STATUS_PAU (1 << 25)
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/* P transmission halted */
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#define TX_DESC_STATUS_TXHA (1 << 24)
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/* Late collision */
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#define TX_DESC_STATUS_LC (1 << 23)
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/* Transmission abort */
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#define TX_DESC_STATUS_TXABT (1 << 22)
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/* No carrier sense */
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#define TX_DESC_STATUS_NCS (1 << 21)
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/* Defer exceed */
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#define TX_DESC_STATUS_EXDEF (1 << 20)
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/* Transmission complete */
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#define TX_DESC_STATUS_TXCP (1 << 19)
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/* Transmission deferred */
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#define TX_DESC_STATUS_DEF (1 << 17)
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/* Transmit interrupt */
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#define TX_DESC_STATUS_TXINTR (1 << 16)
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#define TX_DESC_PKT_LEN(word) extract32((word), 0, 16)
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/* Transmit buffer start address */
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#define TX_DESC_TXBSA(word) ((uint32_t) (word) & ~3u)
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/* Next transmit descriptor start address */
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#define TX_DESC_NTXDSA(word) ((uint32_t) (word) & ~3u)
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/* NPCM7xxEMCRxDesc.status_and_length values */
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/* Owner: 0b00 = cpu, 0b01 = undefined, 0b10 = emc, 0b11 = undefined */
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#define RX_DESC_STATUS_OWNER_SHIFT 30
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#define RX_DESC_STATUS_OWNER_BITSIZE 2
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#define RX_DESC_STATUS_OWNER_MASK (3 << RX_DESC_STATUS_OWNER_SHIFT)
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/* Runt packet */
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#define RX_DESC_STATUS_RP (1 << 22)
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/* Alignment error */
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#define RX_DESC_STATUS_ALIE (1 << 21)
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/* Frame reception complete */
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#define RX_DESC_STATUS_RXGD (1 << 20)
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/* Packet too long */
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#define RX_DESC_STATUS_PTLE (1 << 19)
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/* CRC error */
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#define RX_DESC_STATUS_CRCE (1 << 17)
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/* Receive interrupt */
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#define RX_DESC_STATUS_RXINTR (1 << 16)
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#define RX_DESC_PKT_LEN(word) extract32((word), 0, 16)
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/* Receive buffer start address */
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#define RX_DESC_RXBSA(word) ((uint32_t) (word) & ~3u)
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/* Next receive descriptor start address */
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#define RX_DESC_NRXDSA(word) ((uint32_t) (word) & ~3u)
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/* Minimum packet length, when TX_DESC_FLAG_PADEN is set. */
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#define MIN_PACKET_LENGTH 64
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struct NPCM7xxEMCState {
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/*< private >*/
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SysBusDevice parent;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq tx_irq;
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qemu_irq rx_irq;
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NICState *nic;
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NICConf conf;
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/* 0 or 1, for log messages */
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uint8_t emc_num;
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uint32_t regs[NPCM7XX_NUM_EMC_REGS];
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/*
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* tx is active. Set to true by TSDR and then switches off when out of
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* descriptors. If the TXON bit in REG_MCMDR is off then this is off.
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*/
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bool tx_active;
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/*
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* rx is active. Set to true by RSDR and then switches off when out of
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* descriptors. If the RXON bit in REG_MCMDR is off then this is off.
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*/
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bool rx_active;
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};
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#define TYPE_NPCM7XX_EMC "npcm7xx-emc"
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OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxEMCState, NPCM7XX_EMC)
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#endif /* NPCM7XX_EMC_H */
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