b9b283260e
The RISC-V IOMMU can be modelled as a PCIe device following the guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU as a PCIe device". Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241016204038.649340-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16 lines
841 B
Meson
16 lines
841 B
Meson
riscv_ss = ss.source_set()
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riscv_ss.add(files('boot.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
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riscv_ss.add(files('riscv_hart.c'))
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riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
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riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
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riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
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riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c'))
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hw_arch += {'riscv': riscv_ss}
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