qemu/gdb-xml
Peter Maydell c888f7e0fd target/arm: Use correct GDB XML for M-profile cores
GDB's remote protocol requires M-profile cores to use the feature
name 'org.gnu.gdb.arm.m-profile' instead of the 'org.gnu.gdb.arm.core'
feature used for A- and R-profile cores. We weren't doing this, which
meant GDB treated our M-profile cores like A-profile ones. This mostly
doesn't matter, but for instance means that it doesn't correctly
handle backtraces where an M-profile exception frame is involved.

Ship a copy of GDB's arm-m-profile.xml and use it on the M-profile
cores.  The integer registers have the same offsets as the
arm-core.xml, but register 25 is the M-profile XPSR rather than the
A-profile CPSR, so we need to update arm_cpu_gdb_read_register() and
arm_cpu_gdb_write_register() to handle XSPR reads and writes.

Fixes: https://bugs.launchpad.net/qemu/+bug/1877136
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200507134755.13997-1-peter.maydell@linaro.org
2020-05-14 15:03:08 +01:00
..
aarch64-core.xml
aarch64-fpu.xml
arm-core.xml
arm-m-profile.xml target/arm: Use correct GDB XML for M-profile cores 2020-05-14 15:03:08 +01:00
arm-neon.xml
arm-vfp3.xml
arm-vfp.xml
cf-core.xml
cf-fp.xml
i386-32bit.xml gdbstub: Fix i386/x86_64 machine description and add control registers 2019-02-05 16:50:18 +01:00
i386-64bit.xml gdbstub: Fix i386/x86_64 machine description and add control registers 2019-02-05 16:50:18 +01:00
m68k-core.xml target/m68k: fix gdb for m68xxx 2020-05-06 09:29:26 +01:00
m68k-fp.xml target-m68k: define 96bit FP registers for gdb on 680x0 2017-06-21 22:11:12 +02:00
power64-core.xml
power-altivec.xml
power-core.xml
power-fpu.xml
power-spe.xml
power-vsx.xml
riscv-32bit-cpu.xml RISC-V: Add 32-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-32bit-csr.xml RISC-V: Add 32-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-32bit-fpu.xml RISC-V: Add 64-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-32bit-virtual.xml target/riscv: Expose "priv" register for GDB for reads 2019-10-28 07:47:29 -07:00
riscv-64bit-cpu.xml RISC-V: Add 64-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-64bit-csr.xml RISC-V: Add 64-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-64bit-fpu.xml RISC-V: Add 64-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-64bit-virtual.xml target/riscv: Expose "priv" register for GDB for reads 2019-10-28 07:47:29 -07:00
rx-core.xml target/rx: CPU definitions 2020-03-19 17:58:05 +01:00
s390-acr.xml
s390-cr.xml
s390-fpr.xml
s390-gs.xml s390x/gdb: add gs registers 2017-07-14 12:29:49 +02:00
s390-virt.xml
s390-vx.xml
s390x-core64.xml