c958c51d2e
The NVIDIA BAR0 quirks virtualize the PCI config space mirrors found in device MMIO space. Normally PCI config space is considered a slow path and further optimization is unnecessary, however NVIDIA uses a register here to enable the MSI interrupt to re-trigger. Exiting to QEMU for this MSI-ACK handling can therefore rate limit our interrupt handling. Fortunately the MSI-ACK write is easily detected since the quirk MemoryRegion otherwise has very few accesses, so simply looking for consecutive writes with the same data is sufficient, in this case 10 consecutive writes with the same data and size is arbitrarily chosen. We configure the KVM ioeventfd with data match, so there's no risk of triggering for the wrong data or size, but we do risk that pathological driver behavior might consume all of QEMU's file descriptors, so we cap ourselves to 10 ioeventfds for this purpose. In support of the above, generic ioeventfd infrastructure is added for vfio quirks. This automatically initializes an ioeventfd list per quirk, disables and frees ioeventfds on exit, and allows ioeventfds marked as dynamic to be dropped on device reset. The rationale for this latter feature is that useful ioeventfds may depend on specific driver behavior and since we necessarily place a cap on our use of ioeventfds, a machine reset is a reasonable point at which to assume a new driver and re-profile. Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
133 lines
10 KiB
Plaintext
133 lines
10 KiB
Plaintext
# See docs/devel/tracing.txt for syntax documentation.
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# hw/vfio/pci.c
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vfio_intx_interrupt(const char *name, char line) " (%s) Pin %c"
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vfio_intx_eoi(const char *name) " (%s) EOI"
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vfio_intx_enable_kvm(const char *name) " (%s) KVM INTx accel enabled"
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vfio_intx_disable_kvm(const char *name) " (%s) KVM INTx accel disabled"
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vfio_intx_update(const char *name, int new_irq, int target_irq) " (%s) IRQ moved %d -> %d"
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vfio_intx_enable(const char *name) " (%s)"
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vfio_intx_disable(const char *name) " (%s)"
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vfio_msi_interrupt(const char *name, int index, uint64_t addr, int data) " (%s) vector %d 0x%"PRIx64"/0x%x"
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vfio_msix_vector_do_use(const char *name, int index) " (%s) vector %d used"
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vfio_msix_vector_release(const char *name, int index) " (%s) vector %d released"
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vfio_msix_enable(const char *name) " (%s)"
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vfio_msix_pba_disable(const char *name) " (%s)"
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vfio_msix_pba_enable(const char *name) " (%s)"
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vfio_msix_disable(const char *name) " (%s)"
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vfio_msix_fixup(const char *name, int bar, uint64_t start, uint64_t end) " (%s) MSI-X region %d mmap fixup [0x%"PRIx64" - 0x%"PRIx64"]"
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vfio_msix_relo_cost(const char *name, int bar, uint64_t cost) " (%s) BAR %d cost 0x%"PRIx64""
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vfio_msix_relo(const char *name, int bar, uint64_t offset) " (%s) BAR %d offset 0x%"PRIx64""
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vfio_msi_enable(const char *name, int nr_vectors) " (%s) Enabled %d MSI vectors"
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vfio_msi_disable(const char *name) " (%s)"
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vfio_pci_load_rom(const char *name, unsigned long size, unsigned long offset, unsigned long flags) "Device %s ROM:\n size: 0x%lx, offset: 0x%lx, flags: 0x%lx"
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vfio_rom_read(const char *name, uint64_t addr, int size, uint64_t data) " (%s, 0x%"PRIx64", 0x%x) = 0x%"PRIx64
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vfio_pci_size_rom(const char *name, int size) "%s ROM size 0x%x"
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vfio_vga_write(uint64_t addr, uint64_t data, int size) " (0x%"PRIx64", 0x%"PRIx64", %d)"
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vfio_vga_read(uint64_t addr, int size, uint64_t data) " (0x%"PRIx64", %d) = 0x%"PRIx64
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vfio_pci_read_config(const char *name, int addr, int len, int val) " (%s, @0x%x, len=0x%x) 0x%x"
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vfio_pci_write_config(const char *name, int addr, int val, int len) " (%s, @0x%x, 0x%x, len=0x%x)"
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vfio_msi_setup(const char *name, int pos) "%s PCI MSI CAP @0x%x"
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vfio_msix_early_setup(const char *name, int pos, int table_bar, int offset, int entries) "%s PCI MSI-X CAP @0x%x, BAR %d, offset 0x%x, entries %d"
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vfio_check_pcie_flr(const char *name) "%s Supports FLR via PCIe cap"
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vfio_check_pm_reset(const char *name) "%s Supports PM reset"
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vfio_check_af_flr(const char *name) "%s Supports FLR via AF cap"
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vfio_pci_hot_reset(const char *name, const char *type) " (%s) %s"
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vfio_pci_hot_reset_has_dep_devices(const char *name) "%s: hot reset dependent devices:"
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vfio_pci_hot_reset_dep_devices(int domain, int bus, int slot, int function, int group_id) "\t%04x:%02x:%02x.%x group %d"
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vfio_pci_hot_reset_result(const char *name, const char *result) "%s hot reset: %s"
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vfio_populate_device_config(const char *name, unsigned long size, unsigned long offset, unsigned long flags) "Device %s config:\n size: 0x%lx, offset: 0x%lx, flags: 0x%lx"
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vfio_populate_device_get_irq_info_failure(void) "VFIO_DEVICE_GET_IRQ_INFO failure: %m"
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vfio_realize(const char *name, int group_id) " (%s) group %d"
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vfio_add_ext_cap_dropped(const char *name, uint16_t cap, uint16_t offset) "%s 0x%x@0x%x"
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vfio_pci_reset(const char *name) " (%s)"
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vfio_pci_reset_flr(const char *name) "%s FLR/VFIO_DEVICE_RESET"
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vfio_pci_reset_pm(const char *name) "%s PCI PM Reset"
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vfio_pci_emulated_vendor_id(const char *name, uint16_t val) "%s 0x%04x"
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vfio_pci_emulated_device_id(const char *name, uint16_t val) "%s 0x%04x"
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vfio_pci_emulated_sub_vendor_id(const char *name, uint16_t val) "%s 0x%04x"
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vfio_pci_emulated_sub_device_id(const char *name, uint16_t val) "%s 0x%04x"
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# hw/vfio/pci-quirks.c
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vfio_quirk_rom_blacklisted(const char *name, uint16_t vid, uint16_t did) "%s %04x:%04x"
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vfio_quirk_generic_window_address_write(const char *name, const char * region_name, uint64_t data) "%s %s 0x%"PRIx64
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vfio_quirk_generic_window_data_read(const char *name, const char * region_name, uint64_t data) "%s %s 0x%"PRIx64
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vfio_quirk_generic_window_data_write(const char *name, const char * region_name, uint64_t data) "%s %s 0x%"PRIx64
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vfio_quirk_generic_mirror_read(const char *name, const char * region_name, uint64_t addr, uint64_t data) "%s %s 0x%"PRIx64": 0x%"PRIx64
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vfio_quirk_generic_mirror_write(const char *name, const char * region_name, uint64_t addr, uint64_t data) "%s %s 0x%"PRIx64": 0x%"PRIx64
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vfio_quirk_ati_3c3_read(const char *name, uint64_t data) "%s 0x%"PRIx64
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vfio_quirk_ati_3c3_probe(const char *name) "%s"
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vfio_quirk_ati_bar4_probe(const char *name) "%s"
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vfio_quirk_ati_bar2_probe(const char *name) "%s"
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vfio_quirk_nvidia_3d0_state(const char *name, const char *state) "%s %s"
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vfio_quirk_nvidia_3d0_read(const char *name, uint8_t offset, unsigned size, uint64_t val) " (%s, @0x%x, len=0x%x) 0x%"PRIx64
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vfio_quirk_nvidia_3d0_write(const char *name, uint8_t offset, uint64_t data, unsigned size) "(%s, @0x%x, 0x%"PRIx64", len=0x%x)"
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vfio_quirk_nvidia_3d0_probe(const char *name) "%s"
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vfio_quirk_nvidia_bar5_state(const char *name, const char *state) "%s %s"
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vfio_quirk_nvidia_bar5_probe(const char *name) "%s"
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vfio_quirk_nvidia_bar0_msi_ack(const char *name) "%s"
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vfio_quirk_nvidia_bar0_probe(const char *name) "%s"
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vfio_quirk_rtl8168_fake_latch(const char *name, uint64_t val) "%s 0x%"PRIx64
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vfio_quirk_rtl8168_msix_write(const char *name, uint16_t offset, uint64_t val) "%s MSI-X table write[0x%x]: 0x%"PRIx64
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vfio_quirk_rtl8168_msix_read(const char *name, uint16_t offset, uint64_t val) "%s MSI-X table read[0x%x]: 0x%"PRIx64
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vfio_quirk_rtl8168_probe(const char *name) "%s"
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vfio_quirk_ati_bonaire_reset_skipped(const char *name) "%s"
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vfio_quirk_ati_bonaire_reset_no_smc(const char *name) "%s"
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vfio_quirk_ati_bonaire_reset_timeout(const char *name) "%s"
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vfio_quirk_ati_bonaire_reset_done(const char *name) "%s"
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vfio_quirk_ati_bonaire_reset(const char *name) "%s"
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vfio_ioeventfd_exit(const char *name, uint64_t addr, unsigned size, uint64_t data) "%s+0x%"PRIx64"[%d]:0x%"PRIx64
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vfio_ioeventfd_handler(const char *name, uint64_t addr, unsigned size, uint64_t data) "%s+0x%"PRIx64"[%d] -> 0x%"PRIx64
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vfio_ioeventfd_init(const char *name, uint64_t addr, unsigned size, uint64_t data) "%s+0x%"PRIx64"[%d]:0x%"PRIx64
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vfio_pci_igd_bar4_write(const char *name, uint32_t index, uint32_t data, uint32_t base) "%s [0x%03x] 0x%08x -> 0x%08x"
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vfio_pci_igd_bdsm_enabled(const char *name, int size) "%s %dMB"
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vfio_pci_igd_opregion_enabled(const char *name) "%s"
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vfio_pci_igd_host_bridge_enabled(const char *name) "%s"
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vfio_pci_igd_lpc_bridge_enabled(const char *name) "%s"
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# hw/vfio/common.c
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vfio_region_write(const char *name, int index, uint64_t addr, uint64_t data, unsigned size) " (%s:region%d+0x%"PRIx64", 0x%"PRIx64 ", %d)"
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vfio_region_read(char *name, int index, uint64_t addr, unsigned size, uint64_t data) " (%s:region%d+0x%"PRIx64", %d) = 0x%"PRIx64
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vfio_iommu_map_notify(const char *op, uint64_t iova_start, uint64_t iova_end) "iommu %s @ 0x%"PRIx64" - 0x%"PRIx64
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vfio_listener_region_add_skip(uint64_t start, uint64_t end) "SKIPPING region_add 0x%"PRIx64" - 0x%"PRIx64
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vfio_listener_region_add_iommu(uint64_t start, uint64_t end) "region_add [iommu] 0x%"PRIx64" - 0x%"PRIx64
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vfio_listener_region_add_ram(uint64_t iova_start, uint64_t iova_end, void *vaddr) "region_add [ram] 0x%"PRIx64" - 0x%"PRIx64" [%p]"
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vfio_listener_region_add_no_dma_map(const char *name, uint64_t iova, uint64_t size, uint64_t page_size) "Region \"%s\" 0x%"PRIx64" size=0x%"PRIx64" is not aligned to 0x%"PRIx64" and cannot be mapped for DMA"
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vfio_listener_region_del_skip(uint64_t start, uint64_t end) "SKIPPING region_del 0x%"PRIx64" - 0x%"PRIx64
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vfio_listener_region_del(uint64_t start, uint64_t end) "region_del 0x%"PRIx64" - 0x%"PRIx64
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vfio_disconnect_container(int fd) "close container->fd=%d"
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vfio_put_group(int fd) "close group->fd=%d"
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vfio_get_device(const char * name, unsigned int flags, unsigned int num_regions, unsigned int num_irqs) "Device %s flags: %u, regions: %u, irqs: %u"
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vfio_put_base_device(int fd) "close vdev->fd=%d"
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vfio_region_setup(const char *dev, int index, const char *name, unsigned long flags, unsigned long offset, unsigned long size) "Device %s, region %d \"%s\", flags: 0x%lx, offset: 0x%lx, size: 0x%lx"
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vfio_region_mmap_fault(const char *name, int index, unsigned long offset, unsigned long size, int fault) "Region %s mmaps[%d], [0x%lx - 0x%lx], fault: %d"
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vfio_region_mmap(const char *name, unsigned long offset, unsigned long end) "Region %s [0x%lx - 0x%lx]"
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vfio_region_exit(const char *name, int index) "Device %s, region %d"
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vfio_region_finalize(const char *name, int index) "Device %s, region %d"
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vfio_region_mmaps_set_enabled(const char *name, bool enabled) "Region %s mmaps enabled: %d"
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vfio_region_sparse_mmap_header(const char *name, int index, int nr_areas) "Device %s region %d: %d sparse mmap entries"
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vfio_region_sparse_mmap_entry(int i, unsigned long start, unsigned long end) "sparse entry %d [0x%lx - 0x%lx]"
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vfio_get_dev_region(const char *name, int index, uint32_t type, uint32_t subtype) "%s index %d, %08x/%0x8"
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# hw/vfio/platform.c
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vfio_platform_base_device_init(char *name, int groupid) "%s belongs to group #%d"
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vfio_platform_realize(char *name, char *compat) "vfio device %s, compat = %s"
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vfio_platform_eoi(int pin, int fd) "EOI IRQ pin %d (fd=%d)"
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vfio_platform_intp_mmap_enable(int pin) "IRQ #%d still active, stay in slow path"
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vfio_platform_intp_interrupt(int pin, int fd) "Inject IRQ #%d (fd = %d)"
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vfio_platform_intp_inject_pending_lockheld(int pin, int fd) "Inject pending IRQ #%d (fd = %d)"
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vfio_platform_populate_interrupts(int pin, int count, int flags) "- IRQ index %d: count %d, flags=0x%x"
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vfio_intp_interrupt_set_pending(int index) "irq %d is set PENDING"
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vfio_platform_start_level_irqfd_injection(int index, int fd, int resamplefd) "IRQ index=%d, fd = %d, resamplefd = %d"
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vfio_platform_start_edge_irqfd_injection(int index, int fd) "IRQ index=%d, fd = %d"
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# hw/vfio/spapr.c
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vfio_prereg_listener_region_add_skip(uint64_t start, uint64_t end) "0x%"PRIx64" - 0x%"PRIx64
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vfio_prereg_listener_region_del_skip(uint64_t start, uint64_t end) "0x%"PRIx64" - 0x%"PRIx64
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vfio_prereg_register(uint64_t va, uint64_t size, int ret) "va=0x%"PRIx64" size=0x%"PRIx64" ret=%d"
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vfio_prereg_unregister(uint64_t va, uint64_t size, int ret) "va=0x%"PRIx64" size=0x%"PRIx64" ret=%d"
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vfio_spapr_create_window(int ps, uint64_t ws, uint64_t off) "pageshift=0x%x winsize=0x%"PRIx64" offset=0x%"PRIx64
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vfio_spapr_remove_window(uint64_t off) "offset=0x%"PRIx64
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vfio_spapr_group_attach(int groupfd, int tablefd) "Attached groupfd %d to liobn fd %d"
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