c9410a689f
This patch adds support for the XTheadBa ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
70 lines
3.0 KiB
Plaintext
70 lines
3.0 KiB
Plaintext
#
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# Translation routines for the instructions of the XThead* ISA extensions
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#
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# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
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# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
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#
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# SPDX-License-Identifier: LGPL-2.1-or-later
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#
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# The documentation of the ISA extensions can be found here:
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# https://github.com/T-head-Semi/thead-extension-spec/releases/latest
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# Fields:
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%rd 7:5
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%rs1 15:5
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%rs2 20:5
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# Argument sets
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&r rd rs1 rs2 !extern
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# Formats
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@sfence_vm ....... ..... ..... ... ..... ....... %rs1
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@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
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@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
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# XTheadBa
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# Instead of defining a new encoding, we simply use the decoder to
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# extract the imm[0:1] field and dispatch to separate translation
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# functions (mirroring the `sh[123]add` instructions from Zba and
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# the regular RVI `add` instruction.
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#
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# The only difference between sh[123]add and addsl is that the shift
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# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
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#
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# Note that shift-by-0 is a valid operation according to the manual.
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# This will be equivalent to a regular add.
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add 0000000 ..... ..... 001 ..... 0001011 @r
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th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r
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th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r
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th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r
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# XTheadCmo
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th_dcache_call 0000000 00001 00000 000 00000 0001011
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th_dcache_ciall 0000000 00011 00000 000 00000 0001011
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th_dcache_iall 0000000 00010 00000 000 00000 0001011
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th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm
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th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm
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th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm
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th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm
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th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm
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th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm
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th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm
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th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm
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th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm
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th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm
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th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm
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th_icache_iall 0000000 10000 00000 000 00000 0001011
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th_icache_ialls 0000000 10001 00000 000 00000 0001011
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th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm
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th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm
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th_l2cache_call 0000000 10101 00000 000 00000 0001011
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th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
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th_l2cache_iall 0000000 10110 00000 000 00000 0001011
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# XTheadSync
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th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s
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th_sync 0000000 11000 00000 000 00000 0001011
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th_sync_i 0000000 11010 00000 000 00000 0001011
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th_sync_is 0000000 11011 00000 000 00000 0001011
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th_sync_s 0000000 11001 00000 000 00000 0001011
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