71b4608930
This patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder, function renaming,
removed a TCG temp variable]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
[PMM: cleaned up some unnecessary code in logic_imm_decode_wmask
and added clarifying commentary on what it's actually doing.
Dropped an ext32u that's not needed if we've just done an AND.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
1795 lines
51 KiB
C
1795 lines
51 KiB
C
/*
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* AArch64 translation
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*
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* Copyright (c) 2013 Alexander Graf <agraf@suse.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "tcg-op.h"
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#include "qemu/log.h"
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#include "translate.h"
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#include "qemu/host-utils.h"
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#include "exec/gen-icount.h"
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#include "helper.h"
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#define GEN_HELPER 1
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#include "helper.h"
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static TCGv_i64 cpu_X[32];
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static TCGv_i64 cpu_pc;
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static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
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static const char *regnames[] = {
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"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
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"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
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"x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
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};
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enum a64_shift_type {
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A64_SHIFT_TYPE_LSL = 0,
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A64_SHIFT_TYPE_LSR = 1,
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A64_SHIFT_TYPE_ASR = 2,
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A64_SHIFT_TYPE_ROR = 3
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};
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/* initialize TCG globals. */
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void a64_translate_init(void)
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{
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int i;
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cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUARMState, pc),
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"pc");
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for (i = 0; i < 32; i++) {
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cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUARMState, xregs[i]),
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regnames[i]);
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}
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cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
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cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");
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cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
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cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
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}
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void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint32_t psr = pstate_read(env);
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int i;
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cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
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env->pc, env->xregs[31]);
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for (i = 0; i < 31; i++) {
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cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
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if ((i % 4) == 3) {
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cpu_fprintf(f, "\n");
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} else {
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cpu_fprintf(f, " ");
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}
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}
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cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
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psr,
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psr & PSTATE_N ? 'N' : '-',
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psr & PSTATE_Z ? 'Z' : '-',
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psr & PSTATE_C ? 'C' : '-',
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psr & PSTATE_V ? 'V' : '-');
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cpu_fprintf(f, "\n");
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}
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void gen_a64_set_pc_im(uint64_t val)
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{
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tcg_gen_movi_i64(cpu_pc, val);
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}
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static void gen_exception(int excp)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_movi_i32(tmp, excp);
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gen_helper_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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}
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static void gen_exception_insn(DisasContext *s, int offset, int excp)
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{
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gen_a64_set_pc_im(s->pc - offset);
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gen_exception(excp);
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s->is_jmp = DISAS_EXC;
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}
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static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
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{
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/* No direct tb linking with singlestep or deterministic io */
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if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
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return false;
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}
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/* Only link tbs from inside the same guest page */
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if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
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return false;
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}
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return true;
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}
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static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
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{
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TranslationBlock *tb;
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tb = s->tb;
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if (use_goto_tb(s, n, dest)) {
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tcg_gen_goto_tb(n);
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gen_a64_set_pc_im(dest);
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tcg_gen_exit_tb((tcg_target_long)tb + n);
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s->is_jmp = DISAS_TB_JUMP;
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} else {
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gen_a64_set_pc_im(dest);
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if (s->singlestep_enabled) {
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gen_exception(EXCP_DEBUG);
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}
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tcg_gen_exit_tb(0);
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s->is_jmp = DISAS_JUMP;
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}
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}
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static void unallocated_encoding(DisasContext *s)
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{
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gen_exception_insn(s, 4, EXCP_UDEF);
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}
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#define unsupported_encoding(s, insn) \
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do { \
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qemu_log_mask(LOG_UNIMP, \
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"%s:%d: unsupported instruction encoding 0x%08x " \
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"at pc=%016" PRIx64 "\n", \
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__FILE__, __LINE__, insn, s->pc - 4); \
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unallocated_encoding(s); \
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} while (0);
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static void init_tmp_a64_array(DisasContext *s)
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{
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#ifdef CONFIG_DEBUG_TCG
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int i;
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for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
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TCGV_UNUSED_I64(s->tmp_a64[i]);
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}
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#endif
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s->tmp_a64_count = 0;
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}
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static void free_tmp_a64(DisasContext *s)
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{
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int i;
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for (i = 0; i < s->tmp_a64_count; i++) {
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tcg_temp_free_i64(s->tmp_a64[i]);
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}
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init_tmp_a64_array(s);
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}
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static TCGv_i64 new_tmp_a64(DisasContext *s)
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{
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assert(s->tmp_a64_count < TMP_A64_MAX);
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return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
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}
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static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
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{
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TCGv_i64 t = new_tmp_a64(s);
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tcg_gen_movi_i64(t, 0);
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return t;
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}
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/*
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* Register access functions
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*
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* These functions are used for directly accessing a register in where
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* changes to the final register value are likely to be made. If you
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* need to use a register for temporary calculation (e.g. index type
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* operations) use the read_* form.
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*
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* B1.2.1 Register mappings
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*
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* In instruction register encoding 31 can refer to ZR (zero register) or
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* the SP (stack pointer) depending on context. In QEMU's case we map SP
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* to cpu_X[31] and ZR accesses to a temporary which can be discarded.
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* This is the point of the _sp forms.
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*/
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static TCGv_i64 cpu_reg(DisasContext *s, int reg)
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{
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if (reg == 31) {
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return new_tmp_a64_zero(s);
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} else {
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return cpu_X[reg];
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}
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}
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/* register access for when 31 == SP */
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static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
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{
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return cpu_X[reg];
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}
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/* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
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* representing the register contents. This TCGv is an auto-freed
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* temporary so it need not be explicitly freed, and may be modified.
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*/
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static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
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{
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TCGv_i64 v = new_tmp_a64(s);
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if (reg != 31) {
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if (sf) {
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tcg_gen_mov_i64(v, cpu_X[reg]);
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} else {
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tcg_gen_ext32u_i64(v, cpu_X[reg]);
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}
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} else {
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tcg_gen_movi_i64(v, 0);
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}
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return v;
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}
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/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
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* than the 32 bit equivalent.
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*/
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static inline void gen_set_NZ64(TCGv_i64 result)
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{
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TCGv_i64 flag = tcg_temp_new_i64();
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tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0);
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tcg_gen_trunc_i64_i32(cpu_ZF, flag);
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tcg_gen_shri_i64(flag, result, 32);
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tcg_gen_trunc_i64_i32(cpu_NF, flag);
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tcg_temp_free_i64(flag);
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}
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/* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
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static inline void gen_logic_CC(int sf, TCGv_i64 result)
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{
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if (sf) {
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gen_set_NZ64(result);
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} else {
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tcg_gen_trunc_i64_i32(cpu_ZF, result);
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tcg_gen_trunc_i64_i32(cpu_NF, result);
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}
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tcg_gen_movi_i32(cpu_CF, 0);
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tcg_gen_movi_i32(cpu_VF, 0);
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}
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/*
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* the instruction disassembly implemented here matches
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* the instruction encoding classifications in chapter 3 (C3)
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* of the ARM Architecture Reference Manual (DDI0487A_a)
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*/
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/* C3.2.7 Unconditional branch (immediate)
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* 31 30 26 25 0
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* +----+-----------+-------------------------------------+
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* | op | 0 0 1 0 1 | imm26 |
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* +----+-----------+-------------------------------------+
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*/
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static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
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{
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uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
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if (insn & (1 << 31)) {
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/* C5.6.26 BL Branch with link */
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tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
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}
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/* C5.6.20 B Branch / C5.6.26 BL Branch with link */
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gen_goto_tb(s, 0, addr);
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}
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/* C3.2.1 Compare & branch (immediate)
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* 31 30 25 24 23 5 4 0
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* +----+-------------+----+---------------------+--------+
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* | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
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* +----+-------------+----+---------------------+--------+
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*/
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static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
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{
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unsigned int sf, op, rt;
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uint64_t addr;
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int label_match;
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TCGv_i64 tcg_cmp;
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sf = extract32(insn, 31, 1);
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op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
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rt = extract32(insn, 0, 5);
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addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
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tcg_cmp = read_cpu_reg(s, rt, sf);
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label_match = gen_new_label();
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tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
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tcg_cmp, 0, label_match);
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gen_goto_tb(s, 0, s->pc);
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gen_set_label(label_match);
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gen_goto_tb(s, 1, addr);
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}
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/* C3.2.5 Test & branch (immediate)
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* 31 30 25 24 23 19 18 5 4 0
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* +----+-------------+----+-------+-------------+------+
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* | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
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* +----+-------------+----+-------+-------------+------+
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*/
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static void disas_test_b_imm(DisasContext *s, uint32_t insn)
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{
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unsigned int bit_pos, op, rt;
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uint64_t addr;
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int label_match;
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TCGv_i64 tcg_cmp;
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bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
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op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
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addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
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rt = extract32(insn, 0, 5);
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tcg_cmp = tcg_temp_new_i64();
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tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
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label_match = gen_new_label();
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tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
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tcg_cmp, 0, label_match);
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tcg_temp_free_i64(tcg_cmp);
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gen_goto_tb(s, 0, s->pc);
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gen_set_label(label_match);
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gen_goto_tb(s, 1, addr);
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}
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/* C3.2.2 / C5.6.19 Conditional branch (immediate)
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* 31 25 24 23 5 4 3 0
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* +---------------+----+---------------------+----+------+
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* | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
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* +---------------+----+---------------------+----+------+
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*/
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static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
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{
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unsigned int cond;
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uint64_t addr;
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if ((insn & (1 << 4)) || (insn & (1 << 24))) {
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unallocated_encoding(s);
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return;
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}
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addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
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cond = extract32(insn, 0, 4);
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if (cond < 0x0e) {
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/* genuinely conditional branches */
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int label_match = gen_new_label();
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arm_gen_test_cc(cond, label_match);
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gen_goto_tb(s, 0, s->pc);
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gen_set_label(label_match);
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gen_goto_tb(s, 1, addr);
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} else {
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/* 0xe and 0xf are both "always" conditions */
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gen_goto_tb(s, 0, addr);
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}
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}
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/* C5.6.68 HINT */
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static void handle_hint(DisasContext *s, uint32_t insn,
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unsigned int op1, unsigned int op2, unsigned int crm)
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{
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unsigned int selector = crm << 3 | op2;
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if (op1 != 3) {
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unallocated_encoding(s);
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return;
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}
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switch (selector) {
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case 0: /* NOP */
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return;
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case 1: /* YIELD */
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case 2: /* WFE */
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case 3: /* WFI */
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case 4: /* SEV */
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case 5: /* SEVL */
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/* we treat all as NOP at least for now */
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return;
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default:
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/* default specified as NOP equivalent */
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return;
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}
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}
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/* CLREX, DSB, DMB, ISB */
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static void handle_sync(DisasContext *s, uint32_t insn,
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unsigned int op1, unsigned int op2, unsigned int crm)
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{
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if (op1 != 3) {
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unallocated_encoding(s);
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return;
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}
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switch (op2) {
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case 2: /* CLREX */
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unsupported_encoding(s, insn);
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return;
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case 4: /* DSB */
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case 5: /* DMB */
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case 6: /* ISB */
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/* We don't emulate caches so barriers are no-ops */
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return;
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default:
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unallocated_encoding(s);
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return;
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}
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}
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/* C5.6.130 MSR (immediate) - move immediate to processor state field */
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static void handle_msr_i(DisasContext *s, uint32_t insn,
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unsigned int op1, unsigned int op2, unsigned int crm)
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{
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unsupported_encoding(s, insn);
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}
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/* C5.6.204 SYS */
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static void handle_sys(DisasContext *s, uint32_t insn, unsigned int l,
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unsigned int op1, unsigned int op2,
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unsigned int crn, unsigned int crm, unsigned int rt)
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{
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unsupported_encoding(s, insn);
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}
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/* C5.6.129 MRS - move from system register */
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static void handle_mrs(DisasContext *s, uint32_t insn, unsigned int op0,
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unsigned int op1, unsigned int op2,
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unsigned int crn, unsigned int crm, unsigned int rt)
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{
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unsupported_encoding(s, insn);
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}
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|
|
/* C5.6.131 MSR (register) - move to system register */
|
|
static void handle_msr(DisasContext *s, uint32_t insn, unsigned int op0,
|
|
unsigned int op1, unsigned int op2,
|
|
unsigned int crn, unsigned int crm, unsigned int rt)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* C3.2.4 System
|
|
* 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
|
|
* +---------------------+---+-----+-----+-------+-------+-----+------+
|
|
* | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
|
|
* +---------------------+---+-----+-----+-------+-------+-----+------+
|
|
*/
|
|
static void disas_system(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsigned int l, op0, op1, crn, crm, op2, rt;
|
|
l = extract32(insn, 21, 1);
|
|
op0 = extract32(insn, 19, 2);
|
|
op1 = extract32(insn, 16, 3);
|
|
crn = extract32(insn, 12, 4);
|
|
crm = extract32(insn, 8, 4);
|
|
op2 = extract32(insn, 5, 3);
|
|
rt = extract32(insn, 0, 5);
|
|
|
|
if (op0 == 0) {
|
|
if (l || rt != 31) {
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
switch (crn) {
|
|
case 2: /* C5.6.68 HINT */
|
|
handle_hint(s, insn, op1, op2, crm);
|
|
break;
|
|
case 3: /* CLREX, DSB, DMB, ISB */
|
|
handle_sync(s, insn, op1, op2, crm);
|
|
break;
|
|
case 4: /* C5.6.130 MSR (immediate) */
|
|
handle_msr_i(s, insn, op1, op2, crm);
|
|
break;
|
|
default:
|
|
unallocated_encoding(s);
|
|
break;
|
|
}
|
|
return;
|
|
}
|
|
|
|
if (op0 == 1) {
|
|
/* C5.6.204 SYS */
|
|
handle_sys(s, insn, l, op1, op2, crn, crm, rt);
|
|
} else if (l) { /* op0 > 1 */
|
|
/* C5.6.129 MRS - move from system register */
|
|
handle_mrs(s, insn, op0, op1, op2, crn, crm, rt);
|
|
} else {
|
|
/* C5.6.131 MSR (register) - move to system register */
|
|
handle_msr(s, insn, op0, op1, op2, crn, crm, rt);
|
|
}
|
|
}
|
|
|
|
/* Exception generation */
|
|
static void disas_exc(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* C3.2.7 Unconditional branch (register)
|
|
* 31 25 24 21 20 16 15 10 9 5 4 0
|
|
* +---------------+-------+-------+-------+------+-------+
|
|
* | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
|
|
* +---------------+-------+-------+-------+------+-------+
|
|
*/
|
|
static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsigned int opc, op2, op3, rn, op4;
|
|
|
|
opc = extract32(insn, 21, 4);
|
|
op2 = extract32(insn, 16, 5);
|
|
op3 = extract32(insn, 10, 6);
|
|
rn = extract32(insn, 5, 5);
|
|
op4 = extract32(insn, 0, 5);
|
|
|
|
if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
|
|
switch (opc) {
|
|
case 0: /* BR */
|
|
case 2: /* RET */
|
|
break;
|
|
case 1: /* BLR */
|
|
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
|
|
break;
|
|
case 4: /* ERET */
|
|
case 5: /* DRPS */
|
|
if (rn != 0x1f) {
|
|
unallocated_encoding(s);
|
|
} else {
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
return;
|
|
default:
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
|
|
tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
|
|
s->is_jmp = DISAS_JUMP;
|
|
}
|
|
|
|
/* C3.2 Branches, exception generating and system instructions */
|
|
static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
|
|
{
|
|
switch (extract32(insn, 25, 7)) {
|
|
case 0x0a: case 0x0b:
|
|
case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
|
|
disas_uncond_b_imm(s, insn);
|
|
break;
|
|
case 0x1a: case 0x5a: /* Compare & branch (immediate) */
|
|
disas_comp_b_imm(s, insn);
|
|
break;
|
|
case 0x1b: case 0x5b: /* Test & branch (immediate) */
|
|
disas_test_b_imm(s, insn);
|
|
break;
|
|
case 0x2a: /* Conditional branch (immediate) */
|
|
disas_cond_b_imm(s, insn);
|
|
break;
|
|
case 0x6a: /* Exception generation / System */
|
|
if (insn & (1 << 24)) {
|
|
disas_system(s, insn);
|
|
} else {
|
|
disas_exc(s, insn);
|
|
}
|
|
break;
|
|
case 0x6b: /* Unconditional branch (register) */
|
|
disas_uncond_b_reg(s, insn);
|
|
break;
|
|
default:
|
|
unallocated_encoding(s);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Load/store exclusive */
|
|
static void disas_ldst_excl(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* Load register (literal) */
|
|
static void disas_ld_lit(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* Load/store pair (all forms) */
|
|
static void disas_ldst_pair(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* Load/store register (all forms) */
|
|
static void disas_ldst_reg(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* AdvSIMD load/store multiple structures */
|
|
static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* AdvSIMD load/store single structure */
|
|
static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* C3.3 Loads and stores */
|
|
static void disas_ldst(DisasContext *s, uint32_t insn)
|
|
{
|
|
switch (extract32(insn, 24, 6)) {
|
|
case 0x08: /* Load/store exclusive */
|
|
disas_ldst_excl(s, insn);
|
|
break;
|
|
case 0x18: case 0x1c: /* Load register (literal) */
|
|
disas_ld_lit(s, insn);
|
|
break;
|
|
case 0x28: case 0x29:
|
|
case 0x2c: case 0x2d: /* Load/store pair (all forms) */
|
|
disas_ldst_pair(s, insn);
|
|
break;
|
|
case 0x38: case 0x39:
|
|
case 0x3c: case 0x3d: /* Load/store register (all forms) */
|
|
disas_ldst_reg(s, insn);
|
|
break;
|
|
case 0x0c: /* AdvSIMD load/store multiple structures */
|
|
disas_ldst_multiple_struct(s, insn);
|
|
break;
|
|
case 0x0d: /* AdvSIMD load/store single structure */
|
|
disas_ldst_single_struct(s, insn);
|
|
break;
|
|
default:
|
|
unallocated_encoding(s);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* C3.4.6 PC-rel. addressing
|
|
* 31 30 29 28 24 23 5 4 0
|
|
* +----+-------+-----------+-------------------+------+
|
|
* | op | immlo | 1 0 0 0 0 | immhi | Rd |
|
|
* +----+-------+-----------+-------------------+------+
|
|
*/
|
|
static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsigned int page, rd;
|
|
uint64_t base;
|
|
int64_t offset;
|
|
|
|
page = extract32(insn, 31, 1);
|
|
/* SignExtend(immhi:immlo) -> offset */
|
|
offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2);
|
|
rd = extract32(insn, 0, 5);
|
|
base = s->pc - 4;
|
|
|
|
if (page) {
|
|
/* ADRP (page based) */
|
|
base &= ~0xfff;
|
|
offset <<= 12;
|
|
}
|
|
|
|
tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
|
|
}
|
|
|
|
/* Add/subtract (immediate) */
|
|
static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* The input should be a value in the bottom e bits (with higher
|
|
* bits zero); returns that value replicated into every element
|
|
* of size e in a 64 bit integer.
|
|
*/
|
|
static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
|
|
{
|
|
assert(e != 0);
|
|
while (e < 64) {
|
|
mask |= mask << e;
|
|
e *= 2;
|
|
}
|
|
return mask;
|
|
}
|
|
|
|
/* Return a value with the bottom len bits set (where 0 < len <= 64) */
|
|
static inline uint64_t bitmask64(unsigned int length)
|
|
{
|
|
assert(length > 0 && length <= 64);
|
|
return ~0ULL >> (64 - length);
|
|
}
|
|
|
|
/* Simplified variant of pseudocode DecodeBitMasks() for the case where we
|
|
* only require the wmask. Returns false if the imms/immr/immn are a reserved
|
|
* value (ie should cause a guest UNDEF exception), and true if they are
|
|
* valid, in which case the decoded bit pattern is written to result.
|
|
*/
|
|
static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
|
|
unsigned int imms, unsigned int immr)
|
|
{
|
|
uint64_t mask;
|
|
unsigned e, levels, s, r;
|
|
int len;
|
|
|
|
assert(immn < 2 && imms < 64 && immr < 64);
|
|
|
|
/* The bit patterns we create here are 64 bit patterns which
|
|
* are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
|
|
* 64 bits each. Each element contains the same value: a run
|
|
* of between 1 and e-1 non-zero bits, rotated within the
|
|
* element by between 0 and e-1 bits.
|
|
*
|
|
* The element size and run length are encoded into immn (1 bit)
|
|
* and imms (6 bits) as follows:
|
|
* 64 bit elements: immn = 1, imms = <length of run - 1>
|
|
* 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
|
|
* 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
|
|
* 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
|
|
* 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
|
|
* 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
|
|
* Notice that immn = 0, imms = 11111x is the only combination
|
|
* not covered by one of the above options; this is reserved.
|
|
* Further, <length of run - 1> all-ones is a reserved pattern.
|
|
*
|
|
* In all cases the rotation is by immr % e (and immr is 6 bits).
|
|
*/
|
|
|
|
/* First determine the element size */
|
|
len = 31 - clz32((immn << 6) | (~imms & 0x3f));
|
|
if (len < 1) {
|
|
/* This is the immn == 0, imms == 0x11111x case */
|
|
return false;
|
|
}
|
|
e = 1 << len;
|
|
|
|
levels = e - 1;
|
|
s = imms & levels;
|
|
r = immr & levels;
|
|
|
|
if (s == levels) {
|
|
/* <length of run - 1> mustn't be all-ones. */
|
|
return false;
|
|
}
|
|
|
|
/* Create the value of one element: s+1 set bits rotated
|
|
* by r within the element (which is e bits wide)...
|
|
*/
|
|
mask = bitmask64(s + 1);
|
|
mask = (mask >> r) | (mask << (e - r));
|
|
/* ...then replicate the element over the whole 64 bit value */
|
|
mask = bitfield_replicate(mask, e);
|
|
*result = mask;
|
|
return true;
|
|
}
|
|
|
|
/* C3.4.4 Logical (immediate)
|
|
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
|
|
* +----+-----+-------------+---+------+------+------+------+
|
|
* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
|
|
* +----+-----+-------------+---+------+------+------+------+
|
|
*/
|
|
static void disas_logic_imm(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsigned int sf, opc, is_n, immr, imms, rn, rd;
|
|
TCGv_i64 tcg_rd, tcg_rn;
|
|
uint64_t wmask;
|
|
bool is_and = false;
|
|
|
|
sf = extract32(insn, 31, 1);
|
|
opc = extract32(insn, 29, 2);
|
|
is_n = extract32(insn, 22, 1);
|
|
immr = extract32(insn, 16, 6);
|
|
imms = extract32(insn, 10, 6);
|
|
rn = extract32(insn, 5, 5);
|
|
rd = extract32(insn, 0, 5);
|
|
|
|
if (!sf && is_n) {
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
|
|
if (opc == 0x3) { /* ANDS */
|
|
tcg_rd = cpu_reg(s, rd);
|
|
} else {
|
|
tcg_rd = cpu_reg_sp(s, rd);
|
|
}
|
|
tcg_rn = cpu_reg(s, rn);
|
|
|
|
if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
|
|
/* some immediate field values are reserved */
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
|
|
if (!sf) {
|
|
wmask &= 0xffffffff;
|
|
}
|
|
|
|
switch (opc) {
|
|
case 0x3: /* ANDS */
|
|
case 0x0: /* AND */
|
|
tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
|
|
is_and = true;
|
|
break;
|
|
case 0x1: /* ORR */
|
|
tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
|
|
break;
|
|
case 0x2: /* EOR */
|
|
tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
|
|
break;
|
|
default:
|
|
assert(FALSE); /* must handle all above */
|
|
break;
|
|
}
|
|
|
|
if (!sf && !is_and) {
|
|
/* zero extend final result; we know we can skip this for AND
|
|
* since the immediate had the high 32 bits clear.
|
|
*/
|
|
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
|
|
}
|
|
|
|
if (opc == 3) { /* ANDS */
|
|
gen_logic_CC(sf, tcg_rd);
|
|
}
|
|
}
|
|
|
|
/* Move wide (immediate) */
|
|
static void disas_movw_imm(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* C3.4.2 Bitfield
|
|
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
|
|
* +----+-----+-------------+---+------+------+------+------+
|
|
* | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
|
|
* +----+-----+-------------+---+------+------+------+------+
|
|
*/
|
|
static void disas_bitfield(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len;
|
|
TCGv_i64 tcg_rd, tcg_tmp;
|
|
|
|
sf = extract32(insn, 31, 1);
|
|
opc = extract32(insn, 29, 2);
|
|
n = extract32(insn, 22, 1);
|
|
ri = extract32(insn, 16, 6);
|
|
si = extract32(insn, 10, 6);
|
|
rn = extract32(insn, 5, 5);
|
|
rd = extract32(insn, 0, 5);
|
|
bitsize = sf ? 64 : 32;
|
|
|
|
if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) {
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
|
|
tcg_rd = cpu_reg(s, rd);
|
|
tcg_tmp = read_cpu_reg(s, rn, sf);
|
|
|
|
/* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
|
|
|
|
if (opc != 1) { /* SBFM or UBFM */
|
|
tcg_gen_movi_i64(tcg_rd, 0);
|
|
}
|
|
|
|
/* do the bit move operation */
|
|
if (si >= ri) {
|
|
/* Wd<s-r:0> = Wn<s:r> */
|
|
tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
|
|
pos = 0;
|
|
len = (si - ri) + 1;
|
|
} else {
|
|
/* Wd<32+s-r,32-r> = Wn<s:0> */
|
|
pos = bitsize - ri;
|
|
len = si + 1;
|
|
}
|
|
|
|
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
|
|
|
|
if (opc == 0) { /* SBFM - sign extend the destination field */
|
|
tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
|
|
tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
|
|
}
|
|
|
|
if (!sf) { /* zero extend final result */
|
|
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
|
|
}
|
|
}
|
|
|
|
/* C3.4.3 Extract
|
|
* 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
|
|
* +----+------+-------------+---+----+------+--------+------+------+
|
|
* | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
|
|
* +----+------+-------------+---+----+------+--------+------+------+
|
|
*/
|
|
static void disas_extract(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;
|
|
|
|
sf = extract32(insn, 31, 1);
|
|
n = extract32(insn, 22, 1);
|
|
rm = extract32(insn, 16, 5);
|
|
imm = extract32(insn, 10, 6);
|
|
rn = extract32(insn, 5, 5);
|
|
rd = extract32(insn, 0, 5);
|
|
op21 = extract32(insn, 29, 2);
|
|
op0 = extract32(insn, 21, 1);
|
|
bitsize = sf ? 64 : 32;
|
|
|
|
if (sf != n || op21 || op0 || imm >= bitsize) {
|
|
unallocated_encoding(s);
|
|
} else {
|
|
TCGv_i64 tcg_rd, tcg_rm, tcg_rn;
|
|
|
|
tcg_rd = cpu_reg(s, rd);
|
|
|
|
if (imm) {
|
|
/* OPTME: we can special case rm==rn as a rotate */
|
|
tcg_rm = read_cpu_reg(s, rm, sf);
|
|
tcg_rn = read_cpu_reg(s, rn, sf);
|
|
tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
|
|
tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
|
|
tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
|
|
if (!sf) {
|
|
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
|
|
}
|
|
} else {
|
|
/* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
|
|
* so an extract from bit 0 is a special case.
|
|
*/
|
|
if (sf) {
|
|
tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));
|
|
} else {
|
|
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
|
|
}
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
/* C3.4 Data processing - immediate */
|
|
static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
|
|
{
|
|
switch (extract32(insn, 23, 6)) {
|
|
case 0x20: case 0x21: /* PC-rel. addressing */
|
|
disas_pc_rel_adr(s, insn);
|
|
break;
|
|
case 0x22: case 0x23: /* Add/subtract (immediate) */
|
|
disas_add_sub_imm(s, insn);
|
|
break;
|
|
case 0x24: /* Logical (immediate) */
|
|
disas_logic_imm(s, insn);
|
|
break;
|
|
case 0x25: /* Move wide (immediate) */
|
|
disas_movw_imm(s, insn);
|
|
break;
|
|
case 0x26: /* Bitfield */
|
|
disas_bitfield(s, insn);
|
|
break;
|
|
case 0x27: /* Extract */
|
|
disas_extract(s, insn);
|
|
break;
|
|
default:
|
|
unallocated_encoding(s);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Shift a TCGv src by TCGv shift_amount, put result in dst.
|
|
* Note that it is the caller's responsibility to ensure that the
|
|
* shift amount is in range (ie 0..31 or 0..63) and provide the ARM
|
|
* mandated semantics for out of range shifts.
|
|
*/
|
|
static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf,
|
|
enum a64_shift_type shift_type, TCGv_i64 shift_amount)
|
|
{
|
|
switch (shift_type) {
|
|
case A64_SHIFT_TYPE_LSL:
|
|
tcg_gen_shl_i64(dst, src, shift_amount);
|
|
break;
|
|
case A64_SHIFT_TYPE_LSR:
|
|
tcg_gen_shr_i64(dst, src, shift_amount);
|
|
break;
|
|
case A64_SHIFT_TYPE_ASR:
|
|
if (!sf) {
|
|
tcg_gen_ext32s_i64(dst, src);
|
|
}
|
|
tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount);
|
|
break;
|
|
case A64_SHIFT_TYPE_ROR:
|
|
if (sf) {
|
|
tcg_gen_rotr_i64(dst, src, shift_amount);
|
|
} else {
|
|
TCGv_i32 t0, t1;
|
|
t0 = tcg_temp_new_i32();
|
|
t1 = tcg_temp_new_i32();
|
|
tcg_gen_trunc_i64_i32(t0, src);
|
|
tcg_gen_trunc_i64_i32(t1, shift_amount);
|
|
tcg_gen_rotr_i32(t0, t0, t1);
|
|
tcg_gen_extu_i32_i64(dst, t0);
|
|
tcg_temp_free_i32(t0);
|
|
tcg_temp_free_i32(t1);
|
|
}
|
|
break;
|
|
default:
|
|
assert(FALSE); /* all shift types should be handled */
|
|
break;
|
|
}
|
|
|
|
if (!sf) { /* zero extend final result */
|
|
tcg_gen_ext32u_i64(dst, dst);
|
|
}
|
|
}
|
|
|
|
/* Shift a TCGv src by immediate, put result in dst.
|
|
* The shift amount must be in range (this should always be true as the
|
|
* relevant instructions will UNDEF on bad shift immediates).
|
|
*/
|
|
static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
|
|
enum a64_shift_type shift_type, unsigned int shift_i)
|
|
{
|
|
assert(shift_i < (sf ? 64 : 32));
|
|
|
|
if (shift_i == 0) {
|
|
tcg_gen_mov_i64(dst, src);
|
|
} else {
|
|
TCGv_i64 shift_const;
|
|
|
|
shift_const = tcg_const_i64(shift_i);
|
|
shift_reg(dst, src, sf, shift_type, shift_const);
|
|
tcg_temp_free_i64(shift_const);
|
|
}
|
|
}
|
|
|
|
/* C3.5.10 Logical (shifted register)
|
|
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
|
|
* +----+-----+-----------+-------+---+------+--------+------+------+
|
|
* | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
|
|
* +----+-----+-----------+-------+---+------+--------+------+------+
|
|
*/
|
|
static void disas_logic_reg(DisasContext *s, uint32_t insn)
|
|
{
|
|
TCGv_i64 tcg_rd, tcg_rn, tcg_rm;
|
|
unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;
|
|
|
|
sf = extract32(insn, 31, 1);
|
|
opc = extract32(insn, 29, 2);
|
|
shift_type = extract32(insn, 22, 2);
|
|
invert = extract32(insn, 21, 1);
|
|
rm = extract32(insn, 16, 5);
|
|
shift_amount = extract32(insn, 10, 6);
|
|
rn = extract32(insn, 5, 5);
|
|
rd = extract32(insn, 0, 5);
|
|
|
|
if (!sf && (shift_amount & (1 << 5))) {
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
|
|
tcg_rd = cpu_reg(s, rd);
|
|
|
|
if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) {
|
|
/* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
|
|
* register-register MOV and MVN, so it is worth special casing.
|
|
*/
|
|
tcg_rm = cpu_reg(s, rm);
|
|
if (invert) {
|
|
tcg_gen_not_i64(tcg_rd, tcg_rm);
|
|
if (!sf) {
|
|
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
|
|
}
|
|
} else {
|
|
if (sf) {
|
|
tcg_gen_mov_i64(tcg_rd, tcg_rm);
|
|
} else {
|
|
tcg_gen_ext32u_i64(tcg_rd, tcg_rm);
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
tcg_rm = read_cpu_reg(s, rm, sf);
|
|
|
|
if (shift_amount) {
|
|
shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount);
|
|
}
|
|
|
|
tcg_rn = cpu_reg(s, rn);
|
|
|
|
switch (opc | (invert << 2)) {
|
|
case 0: /* AND */
|
|
case 3: /* ANDS */
|
|
tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
|
|
break;
|
|
case 1: /* ORR */
|
|
tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm);
|
|
break;
|
|
case 2: /* EOR */
|
|
tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm);
|
|
break;
|
|
case 4: /* BIC */
|
|
case 7: /* BICS */
|
|
tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm);
|
|
break;
|
|
case 5: /* ORN */
|
|
tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm);
|
|
break;
|
|
case 6: /* EON */
|
|
tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm);
|
|
break;
|
|
default:
|
|
assert(FALSE);
|
|
break;
|
|
}
|
|
|
|
if (!sf) {
|
|
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
|
|
}
|
|
|
|
if (opc == 3) {
|
|
gen_logic_CC(sf, tcg_rd);
|
|
}
|
|
}
|
|
|
|
/* Add/subtract (extended register) */
|
|
static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* Add/subtract (shifted register) */
|
|
static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* Data-processing (3 source) */
|
|
static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* Add/subtract (with carry) */
|
|
static void disas_adc_sbc(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* Conditional compare (immediate) */
|
|
static void disas_cc_imm(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* Conditional compare (register) */
|
|
static void disas_cc_reg(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* C3.5.6 Conditional select
|
|
* 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
|
|
* +----+----+---+-----------------+------+------+-----+------+------+
|
|
* | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
|
|
* +----+----+---+-----------------+------+------+-----+------+------+
|
|
*/
|
|
static void disas_cond_select(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
|
|
TCGv_i64 tcg_rd, tcg_src;
|
|
|
|
if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
|
|
/* S == 1 or op2<1> == 1 */
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
sf = extract32(insn, 31, 1);
|
|
else_inv = extract32(insn, 30, 1);
|
|
rm = extract32(insn, 16, 5);
|
|
cond = extract32(insn, 12, 4);
|
|
else_inc = extract32(insn, 10, 1);
|
|
rn = extract32(insn, 5, 5);
|
|
rd = extract32(insn, 0, 5);
|
|
|
|
if (rd == 31) {
|
|
/* silly no-op write; until we use movcond we must special-case
|
|
* this to avoid a dead temporary across basic blocks.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
tcg_rd = cpu_reg(s, rd);
|
|
|
|
if (cond >= 0x0e) { /* condition "always" */
|
|
tcg_src = read_cpu_reg(s, rn, sf);
|
|
tcg_gen_mov_i64(tcg_rd, tcg_src);
|
|
} else {
|
|
/* OPTME: we could use movcond here, at the cost of duplicating
|
|
* a lot of the arm_gen_test_cc() logic.
|
|
*/
|
|
int label_match = gen_new_label();
|
|
int label_continue = gen_new_label();
|
|
|
|
arm_gen_test_cc(cond, label_match);
|
|
/* nomatch: */
|
|
tcg_src = cpu_reg(s, rm);
|
|
|
|
if (else_inv && else_inc) {
|
|
tcg_gen_neg_i64(tcg_rd, tcg_src);
|
|
} else if (else_inv) {
|
|
tcg_gen_not_i64(tcg_rd, tcg_src);
|
|
} else if (else_inc) {
|
|
tcg_gen_addi_i64(tcg_rd, tcg_src, 1);
|
|
} else {
|
|
tcg_gen_mov_i64(tcg_rd, tcg_src);
|
|
}
|
|
if (!sf) {
|
|
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
|
|
}
|
|
tcg_gen_br(label_continue);
|
|
/* match: */
|
|
gen_set_label(label_match);
|
|
tcg_src = read_cpu_reg(s, rn, sf);
|
|
tcg_gen_mov_i64(tcg_rd, tcg_src);
|
|
/* continue: */
|
|
gen_set_label(label_continue);
|
|
}
|
|
}
|
|
|
|
static void handle_clz(DisasContext *s, unsigned int sf,
|
|
unsigned int rn, unsigned int rd)
|
|
{
|
|
TCGv_i64 tcg_rd, tcg_rn;
|
|
tcg_rd = cpu_reg(s, rd);
|
|
tcg_rn = cpu_reg(s, rn);
|
|
|
|
if (sf) {
|
|
gen_helper_clz64(tcg_rd, tcg_rn);
|
|
} else {
|
|
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
|
|
tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn);
|
|
gen_helper_clz(tcg_tmp32, tcg_tmp32);
|
|
tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
|
|
tcg_temp_free_i32(tcg_tmp32);
|
|
}
|
|
}
|
|
|
|
static void handle_cls(DisasContext *s, unsigned int sf,
|
|
unsigned int rn, unsigned int rd)
|
|
{
|
|
TCGv_i64 tcg_rd, tcg_rn;
|
|
tcg_rd = cpu_reg(s, rd);
|
|
tcg_rn = cpu_reg(s, rn);
|
|
|
|
if (sf) {
|
|
gen_helper_cls64(tcg_rd, tcg_rn);
|
|
} else {
|
|
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
|
|
tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn);
|
|
gen_helper_cls32(tcg_tmp32, tcg_tmp32);
|
|
tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
|
|
tcg_temp_free_i32(tcg_tmp32);
|
|
}
|
|
}
|
|
|
|
static void handle_rbit(DisasContext *s, unsigned int sf,
|
|
unsigned int rn, unsigned int rd)
|
|
{
|
|
TCGv_i64 tcg_rd, tcg_rn;
|
|
tcg_rd = cpu_reg(s, rd);
|
|
tcg_rn = cpu_reg(s, rn);
|
|
|
|
if (sf) {
|
|
gen_helper_rbit64(tcg_rd, tcg_rn);
|
|
} else {
|
|
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
|
|
tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn);
|
|
gen_helper_rbit(tcg_tmp32, tcg_tmp32);
|
|
tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
|
|
tcg_temp_free_i32(tcg_tmp32);
|
|
}
|
|
}
|
|
|
|
/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
|
|
static void handle_rev64(DisasContext *s, unsigned int sf,
|
|
unsigned int rn, unsigned int rd)
|
|
{
|
|
if (!sf) {
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
|
|
}
|
|
|
|
/* C5.6.149 REV with sf==0, opcode==2
|
|
* C5.6.151 REV32 (sf==1, opcode==2)
|
|
*/
|
|
static void handle_rev32(DisasContext *s, unsigned int sf,
|
|
unsigned int rn, unsigned int rd)
|
|
{
|
|
TCGv_i64 tcg_rd = cpu_reg(s, rd);
|
|
|
|
if (sf) {
|
|
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
|
|
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
|
|
|
|
/* bswap32_i64 requires zero high word */
|
|
tcg_gen_ext32u_i64(tcg_tmp, tcg_rn);
|
|
tcg_gen_bswap32_i64(tcg_rd, tcg_tmp);
|
|
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
|
|
tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
|
|
tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp);
|
|
|
|
tcg_temp_free_i64(tcg_tmp);
|
|
} else {
|
|
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn));
|
|
tcg_gen_bswap32_i64(tcg_rd, tcg_rd);
|
|
}
|
|
}
|
|
|
|
/* C5.6.150 REV16 (opcode==1) */
|
|
static void handle_rev16(DisasContext *s, unsigned int sf,
|
|
unsigned int rn, unsigned int rd)
|
|
{
|
|
TCGv_i64 tcg_rd = cpu_reg(s, rd);
|
|
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
|
|
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
|
|
|
|
tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
|
|
tcg_gen_bswap16_i64(tcg_rd, tcg_tmp);
|
|
|
|
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
|
|
tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
|
|
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
|
|
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16);
|
|
|
|
if (sf) {
|
|
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
|
|
tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
|
|
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
|
|
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16);
|
|
|
|
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48);
|
|
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
|
|
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16);
|
|
}
|
|
|
|
tcg_temp_free_i64(tcg_tmp);
|
|
}
|
|
|
|
/* C3.5.7 Data-processing (1 source)
|
|
* 31 30 29 28 21 20 16 15 10 9 5 4 0
|
|
* +----+---+---+-----------------+---------+--------+------+------+
|
|
* | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
|
|
* +----+---+---+-----------------+---------+--------+------+------+
|
|
*/
|
|
static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsigned int sf, opcode, rn, rd;
|
|
|
|
if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) {
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
|
|
sf = extract32(insn, 31, 1);
|
|
opcode = extract32(insn, 10, 6);
|
|
rn = extract32(insn, 5, 5);
|
|
rd = extract32(insn, 0, 5);
|
|
|
|
switch (opcode) {
|
|
case 0: /* RBIT */
|
|
handle_rbit(s, sf, rn, rd);
|
|
break;
|
|
case 1: /* REV16 */
|
|
handle_rev16(s, sf, rn, rd);
|
|
break;
|
|
case 2: /* REV32 */
|
|
handle_rev32(s, sf, rn, rd);
|
|
break;
|
|
case 3: /* REV64 */
|
|
handle_rev64(s, sf, rn, rd);
|
|
break;
|
|
case 4: /* CLZ */
|
|
handle_clz(s, sf, rn, rd);
|
|
break;
|
|
case 5: /* CLS */
|
|
handle_cls(s, sf, rn, rd);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
|
|
unsigned int rm, unsigned int rn, unsigned int rd)
|
|
{
|
|
TCGv_i64 tcg_n, tcg_m, tcg_rd;
|
|
tcg_rd = cpu_reg(s, rd);
|
|
|
|
if (!sf && is_signed) {
|
|
tcg_n = new_tmp_a64(s);
|
|
tcg_m = new_tmp_a64(s);
|
|
tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn));
|
|
tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm));
|
|
} else {
|
|
tcg_n = read_cpu_reg(s, rn, sf);
|
|
tcg_m = read_cpu_reg(s, rm, sf);
|
|
}
|
|
|
|
if (is_signed) {
|
|
gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m);
|
|
} else {
|
|
gen_helper_udiv64(tcg_rd, tcg_n, tcg_m);
|
|
}
|
|
|
|
if (!sf) { /* zero extend final result */
|
|
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
|
|
}
|
|
}
|
|
|
|
/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
|
|
static void handle_shift_reg(DisasContext *s,
|
|
enum a64_shift_type shift_type, unsigned int sf,
|
|
unsigned int rm, unsigned int rn, unsigned int rd)
|
|
{
|
|
TCGv_i64 tcg_shift = tcg_temp_new_i64();
|
|
TCGv_i64 tcg_rd = cpu_reg(s, rd);
|
|
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
|
|
|
|
tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31);
|
|
shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift);
|
|
tcg_temp_free_i64(tcg_shift);
|
|
}
|
|
|
|
/* C3.5.8 Data-processing (2 source)
|
|
* 31 30 29 28 21 20 16 15 10 9 5 4 0
|
|
* +----+---+---+-----------------+------+--------+------+------+
|
|
* | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
|
|
* +----+---+---+-----------------+------+--------+------+------+
|
|
*/
|
|
static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsigned int sf, rm, opcode, rn, rd;
|
|
sf = extract32(insn, 31, 1);
|
|
rm = extract32(insn, 16, 5);
|
|
opcode = extract32(insn, 10, 6);
|
|
rn = extract32(insn, 5, 5);
|
|
rd = extract32(insn, 0, 5);
|
|
|
|
if (extract32(insn, 29, 1)) {
|
|
unallocated_encoding(s);
|
|
return;
|
|
}
|
|
|
|
switch (opcode) {
|
|
case 2: /* UDIV */
|
|
handle_div(s, false, sf, rm, rn, rd);
|
|
break;
|
|
case 3: /* SDIV */
|
|
handle_div(s, true, sf, rm, rn, rd);
|
|
break;
|
|
case 8: /* LSLV */
|
|
handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
|
|
break;
|
|
case 9: /* LSRV */
|
|
handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd);
|
|
break;
|
|
case 10: /* ASRV */
|
|
handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd);
|
|
break;
|
|
case 11: /* RORV */
|
|
handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd);
|
|
break;
|
|
case 16:
|
|
case 17:
|
|
case 18:
|
|
case 19:
|
|
case 20:
|
|
case 21:
|
|
case 22:
|
|
case 23: /* CRC32 */
|
|
unsupported_encoding(s, insn);
|
|
break;
|
|
default:
|
|
unallocated_encoding(s);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* C3.5 Data processing - register */
|
|
static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
|
|
{
|
|
switch (extract32(insn, 24, 5)) {
|
|
case 0x0a: /* Logical (shifted register) */
|
|
disas_logic_reg(s, insn);
|
|
break;
|
|
case 0x0b: /* Add/subtract */
|
|
if (insn & (1 << 21)) { /* (extended register) */
|
|
disas_add_sub_ext_reg(s, insn);
|
|
} else {
|
|
disas_add_sub_reg(s, insn);
|
|
}
|
|
break;
|
|
case 0x1b: /* Data-processing (3 source) */
|
|
disas_data_proc_3src(s, insn);
|
|
break;
|
|
case 0x1a:
|
|
switch (extract32(insn, 21, 3)) {
|
|
case 0x0: /* Add/subtract (with carry) */
|
|
disas_adc_sbc(s, insn);
|
|
break;
|
|
case 0x2: /* Conditional compare */
|
|
if (insn & (1 << 11)) { /* (immediate) */
|
|
disas_cc_imm(s, insn);
|
|
} else { /* (register) */
|
|
disas_cc_reg(s, insn);
|
|
}
|
|
break;
|
|
case 0x4: /* Conditional select */
|
|
disas_cond_select(s, insn);
|
|
break;
|
|
case 0x6: /* Data-processing */
|
|
if (insn & (1 << 30)) { /* (1 source) */
|
|
disas_data_proc_1src(s, insn);
|
|
} else { /* (2 source) */
|
|
disas_data_proc_2src(s, insn);
|
|
}
|
|
break;
|
|
default:
|
|
unallocated_encoding(s);
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
unallocated_encoding(s);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* C3.6 Data processing - SIMD and floating point */
|
|
static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
|
|
{
|
|
unsupported_encoding(s, insn);
|
|
}
|
|
|
|
/* C3.1 A64 instruction index by encoding */
|
|
static void disas_a64_insn(CPUARMState *env, DisasContext *s)
|
|
{
|
|
uint32_t insn;
|
|
|
|
insn = arm_ldl_code(env, s->pc, s->bswap_code);
|
|
s->insn = insn;
|
|
s->pc += 4;
|
|
|
|
switch (extract32(insn, 25, 4)) {
|
|
case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
|
|
unallocated_encoding(s);
|
|
break;
|
|
case 0x8: case 0x9: /* Data processing - immediate */
|
|
disas_data_proc_imm(s, insn);
|
|
break;
|
|
case 0xa: case 0xb: /* Branch, exception generation and system insns */
|
|
disas_b_exc_sys(s, insn);
|
|
break;
|
|
case 0x4:
|
|
case 0x6:
|
|
case 0xc:
|
|
case 0xe: /* Loads and stores */
|
|
disas_ldst(s, insn);
|
|
break;
|
|
case 0x5:
|
|
case 0xd: /* Data processing - register */
|
|
disas_data_proc_reg(s, insn);
|
|
break;
|
|
case 0x7:
|
|
case 0xf: /* Data processing - SIMD and floating point */
|
|
disas_data_proc_simd_fp(s, insn);
|
|
break;
|
|
default:
|
|
assert(FALSE); /* all 15 cases should be handled above */
|
|
break;
|
|
}
|
|
|
|
/* if we allocated any temporaries, free them here */
|
|
free_tmp_a64(s);
|
|
}
|
|
|
|
void gen_intermediate_code_internal_a64(ARMCPU *cpu,
|
|
TranslationBlock *tb,
|
|
bool search_pc)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
CPUARMState *env = &cpu->env;
|
|
DisasContext dc1, *dc = &dc1;
|
|
CPUBreakpoint *bp;
|
|
uint16_t *gen_opc_end;
|
|
int j, lj;
|
|
target_ulong pc_start;
|
|
target_ulong next_page_start;
|
|
int num_insns;
|
|
int max_insns;
|
|
|
|
pc_start = tb->pc;
|
|
|
|
dc->tb = tb;
|
|
|
|
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
|
|
|
dc->is_jmp = DISAS_NEXT;
|
|
dc->pc = pc_start;
|
|
dc->singlestep_enabled = cs->singlestep_enabled;
|
|
dc->condjmp = 0;
|
|
|
|
dc->aarch64 = 1;
|
|
dc->thumb = 0;
|
|
dc->bswap_code = 0;
|
|
dc->condexec_mask = 0;
|
|
dc->condexec_cond = 0;
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
dc->user = 0;
|
|
#endif
|
|
dc->vfp_enabled = 0;
|
|
dc->vec_len = 0;
|
|
dc->vec_stride = 0;
|
|
|
|
init_tmp_a64_array(dc);
|
|
|
|
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
|
|
lj = -1;
|
|
num_insns = 0;
|
|
max_insns = tb->cflags & CF_COUNT_MASK;
|
|
if (max_insns == 0) {
|
|
max_insns = CF_COUNT_MASK;
|
|
}
|
|
|
|
gen_tb_start();
|
|
|
|
tcg_clear_temp_count();
|
|
|
|
do {
|
|
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
|
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
|
if (bp->pc == dc->pc) {
|
|
gen_exception_insn(dc, 0, EXCP_DEBUG);
|
|
/* Advance PC so that clearing the breakpoint will
|
|
invalidate this TB. */
|
|
dc->pc += 2;
|
|
goto done_generating;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (search_pc) {
|
|
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
|
|
if (lj < j) {
|
|
lj++;
|
|
while (lj < j) {
|
|
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
|
}
|
|
}
|
|
tcg_ctx.gen_opc_pc[lj] = dc->pc;
|
|
tcg_ctx.gen_opc_instr_start[lj] = 1;
|
|
tcg_ctx.gen_opc_icount[lj] = num_insns;
|
|
}
|
|
|
|
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
|
|
gen_io_start();
|
|
}
|
|
|
|
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
|
|
tcg_gen_debug_insn_start(dc->pc);
|
|
}
|
|
|
|
disas_a64_insn(env, dc);
|
|
|
|
if (tcg_check_temp_count()) {
|
|
fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
|
|
dc->pc);
|
|
}
|
|
|
|
/* Translation stops when a conditional branch is encountered.
|
|
* Otherwise the subsequent code could get translated several times.
|
|
* Also stop translation when a page boundary is reached. This
|
|
* ensures prefetch aborts occur at the right place.
|
|
*/
|
|
num_insns++;
|
|
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
|
|
!cs->singlestep_enabled &&
|
|
!singlestep &&
|
|
dc->pc < next_page_start &&
|
|
num_insns < max_insns);
|
|
|
|
if (tb->cflags & CF_LAST_IO) {
|
|
gen_io_end();
|
|
}
|
|
|
|
if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) {
|
|
/* Note that this means single stepping WFI doesn't halt the CPU.
|
|
* For conditional branch insns this is harmless unreachable code as
|
|
* gen_goto_tb() has already handled emitting the debug exception
|
|
* (and thus a tb-jump is not possible when singlestepping).
|
|
*/
|
|
assert(dc->is_jmp != DISAS_TB_JUMP);
|
|
if (dc->is_jmp != DISAS_JUMP) {
|
|
gen_a64_set_pc_im(dc->pc);
|
|
}
|
|
gen_exception(EXCP_DEBUG);
|
|
} else {
|
|
switch (dc->is_jmp) {
|
|
case DISAS_NEXT:
|
|
gen_goto_tb(dc, 1, dc->pc);
|
|
break;
|
|
default:
|
|
case DISAS_JUMP:
|
|
case DISAS_UPDATE:
|
|
/* indicate that the hash table must be used to find the next TB */
|
|
tcg_gen_exit_tb(0);
|
|
break;
|
|
case DISAS_TB_JUMP:
|
|
case DISAS_EXC:
|
|
case DISAS_SWI:
|
|
break;
|
|
case DISAS_WFI:
|
|
/* This is a special case because we don't want to just halt the CPU
|
|
* if trying to debug across a WFI.
|
|
*/
|
|
gen_helper_wfi(cpu_env);
|
|
break;
|
|
}
|
|
}
|
|
|
|
done_generating:
|
|
gen_tb_end(tb, num_insns);
|
|
*tcg_ctx.gen_opc_ptr = INDEX_op_end;
|
|
|
|
#ifdef DEBUG_DISAS
|
|
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
qemu_log("----------------\n");
|
|
qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
|
log_target_disas(env, pc_start, dc->pc - pc_start,
|
|
dc->thumb | (dc->bswap_code << 1));
|
|
qemu_log("\n");
|
|
}
|
|
#endif
|
|
if (search_pc) {
|
|
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
|
|
lj++;
|
|
while (lj <= j) {
|
|
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
|
}
|
|
} else {
|
|
tb->size = dc->pc - pc_start;
|
|
tb->icount = num_insns;
|
|
}
|
|
}
|