Anup Patel c9270e10a5 hw/riscv: Allow creating multiple instances of PLIC ... We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200616032229.766089-3-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-08-25 09:11:35 -07:00
..
boot.c	RISC-V: Support 64 bit start address	2020-07-13 17:25:37 -07:00
Kconfig	hw/char: Initial commit of Ibex UART	2020-06-19 08:24:07 -07:00
meson.build	meson: convert hw/arch*	2020-08-21 06:30:33 -04:00
opentitan.c	error: Eliminate error_propagate() with Coccinelle, part 1	2020-07-10 15:18:08 +02:00
riscv_hart.c	riscv_hart: Fix riscv_harts_realize() error API violations	2020-07-02 06:25:29 +02:00
riscv_htif.c
sifive_clint.c	hw/riscv: Allow creating multiple instances of CLINT	2020-08-25 09:11:35 -07:00
sifive_e_prci.c	sysbus: Convert to sysbus_realize() etc. with Coccinelle	2020-06-15 22:05:28 +02:00
sifive_e.c	hw/riscv: Allow creating multiple instances of PLIC	2020-08-25 09:11:35 -07:00
sifive_gpio.c	hw/riscv: sifive_gpio: Do not blindly trigger output IRQs	2020-06-19 08:25:27 -07:00
sifive_plic.c	hw/riscv: Allow creating multiple instances of PLIC	2020-08-25 09:11:35 -07:00
sifive_test.c	sysbus: Convert to sysbus_realize() etc. with Coccinelle	2020-06-15 22:05:28 +02:00
sifive_u_otp.c
sifive_u_prci.c
sifive_u.c	hw/riscv: Allow creating multiple instances of PLIC	2020-08-25 09:11:35 -07:00
sifive_uart.c
spike.c	hw/riscv: Allow creating multiple instances of CLINT	2020-08-25 09:11:35 -07:00
trace-events
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
virt.c	hw/riscv: Allow creating multiple instances of PLIC	2020-08-25 09:11:35 -07:00