qemu/target
Philippe Mathieu-Daudé c8b69a2a92 target/mips: Remove JR opcode unused arguments
JR opcode (Jump Register) only takes 1 argument, $rs.
JALR (Jump And Link Register) takes 3: $rs, $rd and $hint.

Commit 6af0bf9c7c added their processing into decode_opc() as:

    case 0x08 ... 0x09: /* Jumps */
        gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa);

having both opcodes handled in the same function: gen_compute_branch.

Per JR encoding, both $rd and $hint ('sa') are decoded as zero.

Later this code got extracted to decode_opc_special(),
commit 7a387fffce used definitions instead of magic values:

    case OPC_JR ... OPC_JALR:
        gen_compute_branch(ctx, op1, rs, rd, sa);

Finally commit 0aefa33318 moved OPC_JR out of decode_opc_special,
to a new 'decode_opc_special_legacy' function:

  @@ -15851,6 +15851,9 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
  +    case OPC_JR:
  +        gen_compute_branch(ctx, op1, 4, rs, rd, sa);
  +        break;

  @@ -15933,7 +15936,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
  -    case OPC_JR ... OPC_JALR:
  +    case OPC_JALR:
           gen_compute_branch(ctx, op1, 4, rs, rd, sa);
           break;

Since JR is now handled individually, it is pointless to decode
and pass it unused arguments. Replace them by simple zero value
to avoid confusion with this opcode.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210730225507.2642827-1-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25 12:49:09 +02:00
..
alpha accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
arm target/arm: Add sve-default-vector-length cpu property 2021-07-27 10:57:40 +01:00
avr accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
cris accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
hexagon The Hexagon target was silently failing the SIGSEGV test because 2021-07-26 13:36:51 +01:00
hppa accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
i386 target/i386: Fixed size of constant for Windows 2021-08-13 14:31:49 +02:00
m68k accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
microblaze accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
mips target/mips: Remove JR opcode unused arguments 2021-08-25 12:49:09 +02:00
nios2 target/nios2: Mark raise_exception() as noreturn 2021-07-30 08:23:12 -10:00
openrisc accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
ppc target/ppc: Ease L=0 requirement on cmp/cmpi/cmpl/cmpli for ppc32 2021-07-29 10:59:49 +10:00
riscv accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
rx accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
s390x accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
sh4 accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
sparc accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
tricore accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
xtensa accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00