a7538ca079
The Aspeed machines have many Static Memory Controllers (SMC), up to 8, which can only drive flash memory devices. Commit27a2c66c92("aspeed/smc: Wire CS lines at reset") tried to ease the definitions of these devices by allowing flash devices from the command line to be attached to a SSI bus. For that, the wiring of the CS lines of the Aspeed SMC controller was moved at reset. Two assumptions are made though, first that the device has a SSI_GPIO_CS GPIO line, which is not always the case, and second that it is a flash device. Correct this problem by ensuring that the devices attached to the bus are of the correct flash type. This fixes a QEMU abort when devices without a CS line, such as the max111x, are passed on the command line. While at it, export TYPE_M25P80 used in the Xilinx Versal Virtual machine. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2228 Fixes:27a2c66c92("aspeed/smc: Wire CS lines at reset") Reported-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> [ clg: minor fixes in the commit log ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
86 lines
2.7 KiB
C
86 lines
2.7 KiB
C
#ifndef HW_FLASH_H
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#define HW_FLASH_H
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/* NOR flash devices */
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#include "exec/hwaddr.h"
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#include "qom/object.h"
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/* pflash_cfi01.c */
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#define TYPE_PFLASH_CFI01 "cfi.pflash01"
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OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI01, PFLASH_CFI01)
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PFlashCFI01 *pflash_cfi01_register(hwaddr base,
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const char *name,
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hwaddr size,
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BlockBackend *blk,
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uint32_t sector_len,
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int width,
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uint16_t id0, uint16_t id1,
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uint16_t id2, uint16_t id3,
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int be);
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BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl);
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MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl);
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void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo);
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/* pflash_cfi02.c */
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#define TYPE_PFLASH_CFI02 "cfi.pflash02"
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OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI02, PFLASH_CFI02)
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PFlashCFI02 *pflash_cfi02_register(hwaddr base,
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const char *name,
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hwaddr size,
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BlockBackend *blk,
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uint32_t sector_len,
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int nb_mappings,
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int width,
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uint16_t id0, uint16_t id1,
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uint16_t id2, uint16_t id3,
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uint16_t unlock_addr0,
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uint16_t unlock_addr1,
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int be);
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/* nand.c */
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DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id);
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void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
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uint8_t ce, uint8_t wp, uint8_t gnd);
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void nand_getpins(DeviceState *dev, int *rb);
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void nand_setio(DeviceState *dev, uint32_t value);
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uint32_t nand_getio(DeviceState *dev);
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uint32_t nand_getbuswidth(DeviceState *dev);
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#define NAND_MFR_TOSHIBA 0x98
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#define NAND_MFR_SAMSUNG 0xec
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#define NAND_MFR_FUJITSU 0x04
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#define NAND_MFR_NATIONAL 0x8f
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#define NAND_MFR_RENESAS 0x07
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#define NAND_MFR_STMICRO 0x20
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#define NAND_MFR_HYNIX 0xad
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#define NAND_MFR_MICRON 0x2c
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/* onenand.c */
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void *onenand_raw_otp(DeviceState *onenand_device);
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/* ecc.c */
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typedef struct {
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uint8_t cp; /* Column parity */
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uint16_t lp[2]; /* Line parity */
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uint16_t count;
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} ECCState;
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uint8_t ecc_digest(ECCState *s, uint8_t sample);
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void ecc_reset(ECCState *s);
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extern const VMStateDescription vmstate_ecc_state;
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/* m25p80.c */
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#define TYPE_M25P80 "m25p80-generic"
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BlockBackend *m25p80_get_blk(DeviceState *dev);
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#endif
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