Bin Meng 81e94379f7 riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet ... In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-09-17 08:42:49 -07:00
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boot.h
riscv_hart.h	riscv: hart: Add a "hartid-base" property to RISC-V hart array	2019-09-17 08:42:47 -07:00
riscv_htif.h
sifive_clint.h
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e_prci.h	riscv: sifive_e: prci: Update the PRCI register block size	2019-09-17 08:42:46 -07:00
sifive_e.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_gpio.h
sifive_plic.h
sifive_test.h
sifive_u_otp.h	riscv: sifive: Implement a model for SiFive FU540 OTP	2019-09-17 08:42:49 -07:00
sifive_u_prci.h	riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes	2019-09-17 08:42:48 -07:00
sifive_u.h	riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet	2019-09-17 08:42:49 -07:00
sifive_uart.h
spike.h
virt.h