c5619bf9e8
Grouping (GICv2) and Security Extensions change the behavior of IAR reads. Acknowledging Group0 interrupts is only allowed from Secure state and acknowledging Group1 interrupts from Secure state is only allowed if AckCtl bit is set. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-14-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-14-git-send-email-greg.bellows@linaro.org [PMM: simplify significantly by reusing the existing gic_get_current_pending_irq() rather than reimplementing the same logic here] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
104 lines
4.4 KiB
C
104 lines
4.4 KiB
C
/*
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* ARM GIC support - internal interfaces
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_ARM_GIC_INTERNAL_H
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#define QEMU_ARM_GIC_INTERNAL_H
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#include "hw/intc/arm_gic.h"
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#define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))
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/* The NVIC has 16 internal vectors. However these are not exposed
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through the normal GIC interface. */
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#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0)
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#define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
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#define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
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#define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
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#define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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#define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
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#define GIC_SET_MODEL(irq) s->irq_state[irq].model = true
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#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level |= (cm)
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#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
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#define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = true
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#define GIC_CLEAR_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = false
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#define GIC_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger)
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#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
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s->priority1[irq][cpu] : \
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s->priority2[(irq) - GIC_INTERNAL])
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#define GIC_TARGET(irq) s->irq_target[irq]
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#define GIC_CLEAR_GROUP(irq, cm) (s->irq_state[irq].group &= ~(cm))
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#define GIC_SET_GROUP(irq, cm) (s->irq_state[irq].group |= (cm))
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#define GIC_TEST_GROUP(irq, cm) ((s->irq_state[irq].group & (cm)) != 0)
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#define GICD_CTLR_EN_GRP0 (1U << 0)
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#define GICD_CTLR_EN_GRP1 (1U << 1)
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#define GICC_CTLR_EN_GRP0 (1U << 0)
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#define GICC_CTLR_EN_GRP1 (1U << 1)
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#define GICC_CTLR_ACK_CTL (1U << 2)
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#define GICC_CTLR_FIQ_EN (1U << 3)
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#define GICC_CTLR_CBPR (1U << 4) /* GICv1: SBPR */
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#define GICC_CTLR_EOIMODE (1U << 9)
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#define GICC_CTLR_EOIMODE_NS (1U << 10)
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/* Valid bits for GICC_CTLR for GICv1, v1 with security extensions,
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* GICv2 and GICv2 with security extensions:
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*/
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#define GICC_CTLR_V1_MASK 0x1
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#define GICC_CTLR_V1_S_MASK 0x1f
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#define GICC_CTLR_V2_MASK 0x21f
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#define GICC_CTLR_V2_S_MASK 0x61f
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/* The special cases for the revision property: */
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#define REV_11MPCORE 0
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#define REV_NVIC 0xffffffff
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void gic_set_pending_private(GICState *s, int cpu, int irq);
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uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs);
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void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs);
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void gic_update(GICState *s);
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void gic_init_irqs_and_distributor(GICState *s);
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void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val,
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MemTxAttrs attrs);
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static inline bool gic_test_pending(GICState *s, int irq, int cm)
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{
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if (s->revision == REV_NVIC || s->revision == REV_11MPCORE) {
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return s->irq_state[irq].pending & cm;
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} else {
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/* Edge-triggered interrupts are marked pending on a rising edge, but
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* level-triggered interrupts are either considered pending when the
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* level is active or if software has explicitly written to
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* GICD_ISPENDR to set the state pending.
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*/
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return (s->irq_state[irq].pending & cm) ||
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(!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_LEVEL(irq, cm));
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}
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}
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#endif /* !QEMU_ARM_GIC_INTERNAL_H */
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