e4fdf9df5b
Populate this new method for all targets. Always match the result that would be given by cpu_get_tb_cpu_state, as we will want these values to correspond in the logs. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (target/sparc) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- Cc: Eduardo Habkost <eduardo@habkost.net> (supporter:Machine core) Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> (supporter:Machine core) Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> (reviewer:Machine core) Cc: Yanan Wang <wangyanan55@huawei.com> (reviewer:Machine core) Cc: Michael Rolnik <mrolnik@gmail.com> (maintainer:AVR TCG CPUs) Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> (maintainer:CRIS TCG CPUs) Cc: Taylor Simpson <tsimpson@quicinc.com> (supporter:Hexagon TCG CPUs) Cc: Song Gao <gaosong@loongson.cn> (maintainer:LoongArch TCG CPUs) Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn> (maintainer:LoongArch TCG CPUs) Cc: Laurent Vivier <laurent@vivier.eu> (maintainer:M68K TCG CPUs) Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs) Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> (reviewer:MIPS TCG CPUs) Cc: Chris Wulff <crwulff@gmail.com> (maintainer:NiosII TCG CPUs) Cc: Marek Vasut <marex@denx.de> (maintainer:NiosII TCG CPUs) Cc: Stafford Horne <shorne@gmail.com> (odd fixer:OpenRISC TCG CPUs) Cc: Yoshinori Sato <ysato@users.sourceforge.jp> (reviewer:RENESAS RX CPUs) Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (maintainer:SPARC TCG CPUs) Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (maintainer:TriCore TCG CPUs) Cc: Max Filippov <jcmvbkbc@gmail.com> (maintainer:Xtensa TCG CPUs) Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs) Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs) Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
271 lines
8.0 KiB
C
271 lines
8.0 KiB
C
/*
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* QEMU Xtensa CPU
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*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "fpu/softfloat.h"
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#include "qemu/module.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-clock.h"
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static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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cpu->env.pc = value;
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}
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static vaddr xtensa_cpu_get_pc(CPUState *cs)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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return cpu->env.pc;
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}
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static bool xtensa_cpu_has_work(CPUState *cs)
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{
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#ifndef CONFIG_USER_ONLY
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XtensaCPU *cpu = XTENSA_CPU(cs);
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return !cpu->env.runstall && cpu->env.pending_irq_level;
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#else
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return true;
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#endif
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}
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#ifdef CONFIG_USER_ONLY
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static bool abi_call0;
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void xtensa_set_abi_call0(void)
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{
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abi_call0 = true;
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}
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bool xtensa_abi_call0(void)
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{
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return abi_call0;
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}
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#endif
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static void xtensa_cpu_reset(DeviceState *dev)
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{
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CPUState *s = CPU(dev);
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XtensaCPU *cpu = XTENSA_CPU(s);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
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CPUXtensaState *env = &cpu->env;
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bool dfpu = xtensa_option_enabled(env->config,
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XTENSA_OPTION_DFP_COPROCESSOR);
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xcc->parent_reset(dev);
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env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
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env->sregs[LITBASE] &= ~1;
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#ifndef CONFIG_USER_ONLY
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env->sregs[PS] = xtensa_option_enabled(env->config,
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XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
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env->pending_irq_level = 0;
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#else
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env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
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if (xtensa_option_enabled(env->config,
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XTENSA_OPTION_WINDOWED_REGISTER) &&
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!xtensa_abi_call0()) {
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env->sregs[PS] |= PS_WOE;
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}
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env->sregs[CPENABLE] = 0xff;
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#endif
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env->sregs[VECBASE] = env->config->vecbase;
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env->sregs[IBREAKENABLE] = 0;
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env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
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env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
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XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
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env->sregs[CONFIGID0] = env->config->configid[0];
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env->sregs[CONFIGID1] = env->config->configid[1];
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env->exclusive_addr = -1;
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#ifndef CONFIG_USER_ONLY
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reset_mmu(env);
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s->halted = env->runstall;
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#endif
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set_no_signaling_nans(!dfpu, &env->fp_status);
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set_use_first_nan(!dfpu, &env->fp_status);
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}
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static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
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object_class_is_abstract(oc)) {
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return NULL;
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}
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return oc;
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}
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static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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info->private_data = cpu->env.config->isa;
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info->print_insn = print_insn_xtensa;
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}
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static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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#ifndef CONFIG_USER_ONLY
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xtensa_irq_init(&XTENSA_CPU(dev)->env);
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#endif
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
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qemu_init_vcpu(cs);
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xcc->parent_realize(dev, errp);
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}
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static void xtensa_cpu_initfn(Object *obj)
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{
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XtensaCPU *cpu = XTENSA_CPU(obj);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
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CPUXtensaState *env = &cpu->env;
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cpu_set_cpustate_pointers(cpu);
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env->config = xcc->config;
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#ifndef CONFIG_USER_ONLY
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env->address_space_er = g_malloc(sizeof(*env->address_space_er));
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env->system_er = g_malloc(sizeof(*env->system_er));
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memory_region_init_io(env->system_er, obj, NULL, env, "er",
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UINT64_C(0x100000000));
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address_space_init(env->address_space_er, env->system_er, "ER");
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cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
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clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000);
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#endif
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}
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XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
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{
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DeviceState *cpu;
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cpu = DEVICE(object_new(cpu_type));
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qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
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qdev_realize(cpu, NULL, &error_abort);
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return XTENSA_CPU(cpu);
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}
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#ifndef CONFIG_USER_ONLY
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static const VMStateDescription vmstate_xtensa_cpu = {
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.name = "cpu",
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.unmigratable = 1,
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};
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#include "hw/core/sysemu-cpu-ops.h"
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static const struct SysemuCPUOps xtensa_sysemu_ops = {
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.get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
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};
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#endif
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#include "hw/core/tcg-cpu-ops.h"
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static const struct TCGCPUOps xtensa_tcg_ops = {
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.initialize = xtensa_translate_init,
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.debug_excp_handler = xtensa_breakpoint_handler,
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#ifndef CONFIG_USER_ONLY
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.tlb_fill = xtensa_cpu_tlb_fill,
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.cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
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.do_interrupt = xtensa_cpu_do_interrupt,
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.do_transaction_failed = xtensa_cpu_do_transaction_failed,
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.do_unaligned_access = xtensa_cpu_do_unaligned_access,
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#endif /* !CONFIG_USER_ONLY */
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};
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static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
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device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
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&xcc->parent_realize);
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device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
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cc->class_by_name = xtensa_cpu_class_by_name;
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cc->has_work = xtensa_cpu_has_work;
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cc->dump_state = xtensa_cpu_dump_state;
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cc->set_pc = xtensa_cpu_set_pc;
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cc->get_pc = xtensa_cpu_get_pc;
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cc->gdb_read_register = xtensa_cpu_gdb_read_register;
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cc->gdb_write_register = xtensa_cpu_gdb_write_register;
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cc->gdb_stop_before_watchpoint = true;
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#ifndef CONFIG_USER_ONLY
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cc->sysemu_ops = &xtensa_sysemu_ops;
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dc->vmsd = &vmstate_xtensa_cpu;
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#endif
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cc->disas_set_info = xtensa_cpu_disas_set_info;
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cc->tcg_ops = &xtensa_tcg_ops;
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}
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static const TypeInfo xtensa_cpu_type_info = {
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.name = TYPE_XTENSA_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(XtensaCPU),
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.instance_init = xtensa_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(XtensaCPUClass),
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.class_init = xtensa_cpu_class_init,
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};
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static void xtensa_cpu_register_types(void)
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{
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type_register_static(&xtensa_cpu_type_info);
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}
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type_init(xtensa_cpu_register_types)
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