Daniel Henrique Barboza 3ca78c0689 target/riscv/kvm: add RVV and Vector CSR regs ...

Add support for RVV and Vector CSR KVM regs vstart, vl and vtype.

Support for vregs[] requires KVM side changes and an extra reg (vlenb)
and will be added later.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218204321.75757-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2024-01-10 18:47:47 +10:00

..

kvm_riscv.h

…

kvm-cpu.c

target/riscv/kvm: add RVV and Vector CSR regs

2024-01-10 18:47:47 +10:00

meson.build

…