a62bf59fd9
Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
117 lines
3.8 KiB
C
117 lines
3.8 KiB
C
/*
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* i.MX GPT Timer
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*
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* Copyright (c) 2008 OK Labs
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* Copyright (c) 2011 NICTA Pty Ltd
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* Originally written by Hans Jiang
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* Updated by Peter Chubb
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef IMX_GPT_H
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#define IMX_GPT_H
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#include "hw/sysbus.h"
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#include "hw/ptimer.h"
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#include "hw/misc/imx_ccm.h"
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/*
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* GPT : General purpose timer
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*
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* This timer counts up continuously while it is enabled, resetting itself
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* to 0 when it reaches GPT_TIMER_MAX (in freerun mode) or when it
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* reaches the value of one of the ocrX (in periodic mode).
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*/
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#define GPT_TIMER_MAX 0XFFFFFFFFUL
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/* Control register. Not all of these bits have any effect (yet) */
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#define GPT_CR_EN (1 << 0) /* GPT Enable */
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#define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
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#define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
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#define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
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#define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
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#define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
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#define GPT_CR_CLKSRC_SHIFT (6)
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#define GPT_CR_CLKSRC_MASK (0x7)
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#define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
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#define GPT_CR_SWR (1 << 15) /* Software Reset */
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#define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
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#define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */
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#define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
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#define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
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#define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
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#define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */
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#define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */
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#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
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#define GPT_SR_OF1 (1 << 0)
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#define GPT_SR_OF2 (1 << 1)
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#define GPT_SR_OF3 (1 << 2)
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#define GPT_SR_ROV (1 << 5)
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#define GPT_IR_OF1IE (1 << 0)
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#define GPT_IR_OF2IE (1 << 1)
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#define GPT_IR_OF3IE (1 << 2)
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#define GPT_IR_ROVIE (1 << 5)
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#define TYPE_IMX25_GPT "imx25.gpt"
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#define TYPE_IMX31_GPT "imx31.gpt"
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#define TYPE_IMX6_GPT "imx6.gpt"
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#define TYPE_IMX7_GPT "imx7.gpt"
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#define TYPE_IMX_GPT TYPE_IMX25_GPT
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#define IMX_GPT(obj) OBJECT_CHECK(IMXGPTState, (obj), TYPE_IMX_GPT)
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typedef struct IMXGPTState{
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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ptimer_state *timer;
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MemoryRegion iomem;
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IMXCCMState *ccm;
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uint32_t cr;
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uint32_t pr;
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uint32_t sr;
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uint32_t ir;
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uint32_t ocr1;
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uint32_t ocr2;
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uint32_t ocr3;
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uint32_t icr1;
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uint32_t icr2;
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uint32_t cnt;
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uint32_t next_timeout;
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uint32_t next_int;
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uint32_t freq;
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qemu_irq irq;
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const IMXClk *clocks;
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} IMXGPTState;
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#endif /* IMX_GPT_H */
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