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qemu/target/riscv/insn_trans
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Kito Cheng 3a4a43e4e2 target/riscv: rvb: add/shift with prefix zero-extend 
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-16-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08 09:59:45 +10:00
..
trans_privileged.c.inc
riscv: Add semihosting support
2021-01-18 10:05:06 +00:00
trans_rva.c.inc
target/riscv: Consolidate RV32/64 32-bit instructions
2021-05-11 20:02:07 +10:00
trans_rvb.c.inc
target/riscv: rvb: add/shift with prefix zero-extend
2021-06-08 09:59:45 +10:00
trans_rvd.c.inc
target/riscv: Consolidate RV32/64 32-bit instructions
2021-05-11 20:02:07 +10:00
trans_rvf.c.inc
target/riscv: Consolidate RV32/64 32-bit instructions
2021-05-11 20:02:07 +10:00
trans_rvh.c.inc
target/riscv: Consolidate RV32/64 32-bit instructions
2021-05-11 20:02:07 +10:00
trans_rvi.c.inc
target/riscv: add gen_shifti() and gen_shiftiw() helper functions
2021-06-08 09:59:44 +10:00
trans_rvm.c.inc
target/riscv: Consolidate RV32/64 32-bit instructions
2021-05-11 20:02:07 +10:00
trans_rvv.c.inc
target/riscv: Pass the same value to oprsz and maxsz.
2021-06-08 09:59:43 +10:00