mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
qemu/include/hw/riscv
History
Alistair Francis c407784291 hw/riscv: Add a riscv_is_32_bit() function 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 4c6a85dfb6dd470aa79356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com
2020-10-22 12:00:22 -07:00
..
boot_opensbi.h
…
boot.h
hw/riscv: Add a riscv_is_32_bit() function
2020-10-22 12:00:22 -07:00
microchip_pfsoc.h
hw/riscv: microchip_pfsoc: Hook GPIO controllers
2020-09-09 15:54:19 -07:00
numa.h
…
opentitan.h
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
riscv_hart.h
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
sifive_cpu.h
…
sifive_e.h
sifive_e: Rename memmap enum constants
2020-09-18 13:49:48 -04:00
sifive_u.h
hw/riscv: sifive_u: Allow specifying the CPU
2020-10-22 12:00:22 -07:00
spike.h
Use DECLARE_*CHECKER* macros
2020-09-09 09:27:09 -04:00
virt.h
Use DECLARE_*CHECKER* macros
2020-09-09 09:27:09 -04:00