c3f21b065a
The CPU interface changes to support vLPIs are fairly minor: in the parts of the code that currently look at the list registers to determine the highest priority pending virtual interrupt, we must also look at the highest priority pending vLPI. To do this we change hppvi_index() to check the vLPI and return a special-case value if that is the right virtual interrupt to take. The callsites (which handle HPPIR and IAR registers and the "raise vIRQ and vFIQ lines" code) then have to handle this special-case value. This commit includes two interfaces with the as-yet-unwritten redistributor code: * the new GICv3CPUState::hppvlpi will be set by the redistributor (in the same way as the existing hpplpi does for physical LPIs) * when the CPU interface acknowledges a vLPI it needs to set it to non-pending; the new gicv3_redist_vlpi_pending() function (which matches the existing gicv3_redist_lpi_pending() used for physical LPIs) is a stub that will be filled in later Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-26-peter.maydell@linaro.org |
||
|---|---|---|
| .. | ||
| allwinner-a10-pic.h | ||
| arm_gic_common.h | ||
| arm_gic.h | ||
| arm_gicv3_common.h | ||
| arm_gicv3_its_common.h | ||
| arm_gicv3.h | ||
| armv7m_nvic.h | ||
| aspeed_vic.h | ||
| bcm2835_ic.h | ||
| bcm2836_control.h | ||
| exynos4210_combiner.h | ||
| exynos4210_gic.h | ||
| goldfish_pic.h | ||
| heathrow_pic.h | ||
| i8259.h | ||
| imx_avic.h | ||
| imx_gpcv2.h | ||
| intc.h | ||
| loongson_liointc.h | ||
| m68k_irqc.h | ||
| mips_gic.h | ||
| ppc-uic.h | ||
| realview_gic.h | ||
| riscv_aclint.h | ||
| riscv_aplic.h | ||
| riscv_imsic.h | ||
| rx_icu.h | ||
| sifive_plic.h | ||
| xlnx-pmu-iomod-intc.h | ||
| xlnx-zynqmp-ipi.h | ||