c3d25271b2
The load/store API eases code review. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-3-stephen.checkoway@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Extracted from bigger patch] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
757 lines
23 KiB
C
757 lines
23 KiB
C
/*
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* CFI parallel flash with AMD command set emulation
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*
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* Copyright (c) 2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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* Supported commands/modes are:
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* - flash read
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* - flash write
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* - flash ID read
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* - sector erase
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* - chip erase
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* - unlock bypass command
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* - CFI queries
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*
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* It does not support flash interleaving.
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* It does not implement boot blocs with reduced size
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* It does not implement software data protection as found in many real chips
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* It does not implement erase suspend/resume commands
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* It does not implement multiple sectors erase
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/block/block.h"
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#include "hw/block/flash.h"
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#include "qapi/error.h"
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#include "qemu/timer.h"
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#include "sysemu/block-backend.h"
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#include "qemu/host-utils.h"
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#include "qemu/module.h"
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#include "hw/sysbus.h"
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#include "trace.h"
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#define PFLASH_DEBUG false
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#define DPRINTF(fmt, ...) \
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do { \
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if (PFLASH_DEBUG) { \
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fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__); \
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} \
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} while (0)
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#define PFLASH_LAZY_ROMD_THRESHOLD 42
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/* Special write cycles for CFI queries. */
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enum {
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WCYCLE_CFI = 7,
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};
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struct PFlashCFI02 {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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BlockBackend *blk;
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uint32_t sector_len;
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uint32_t nb_blocs;
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uint32_t chip_len;
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uint8_t mappings;
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uint8_t width;
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uint8_t be;
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int wcycle; /* if 0, the flash is read normally */
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int bypass;
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int ro;
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uint8_t cmd;
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uint8_t status;
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/* FIXME: implement array device properties */
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uint16_t ident0;
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uint16_t ident1;
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uint16_t ident2;
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uint16_t ident3;
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uint16_t unlock_addr0;
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uint16_t unlock_addr1;
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uint8_t cfi_table[0x52];
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QEMUTimer timer;
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/* The device replicates the flash memory across its memory space. Emulate
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* that by having a container (.mem) filled with an array of aliases
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* (.mem_mappings) pointing to the flash memory (.orig_mem).
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*/
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MemoryRegion mem;
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MemoryRegion *mem_mappings; /* array; one per mapping */
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MemoryRegion orig_mem;
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int rom_mode;
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int read_counter; /* used for lazy switch-back to rom mode */
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char *name;
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void *storage;
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};
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/*
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* Toggle status bit DQ7.
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*/
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static inline void toggle_dq7(PFlashCFI02 *pfl)
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{
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pfl->status ^= 0x80;
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}
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/*
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* Set status bit DQ7 to bit 7 of value.
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*/
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static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value)
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{
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pfl->status &= 0x7F;
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pfl->status |= value & 0x80;
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}
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/*
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* Toggle status bit DQ6.
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*/
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static inline void toggle_dq6(PFlashCFI02 *pfl)
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{
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pfl->status ^= 0x40;
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}
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/*
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* Set up replicated mappings of the same region.
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*/
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static void pflash_setup_mappings(PFlashCFI02 *pfl)
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{
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unsigned i;
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hwaddr size = memory_region_size(&pfl->orig_mem);
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memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
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pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
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for (i = 0; i < pfl->mappings; ++i) {
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memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
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"pflash-alias", &pfl->orig_mem, 0, size);
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memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
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}
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}
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static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode)
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{
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memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
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pfl->rom_mode = rom_mode;
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}
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static void pflash_timer (void *opaque)
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{
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PFlashCFI02 *pfl = opaque;
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trace_pflash_timer_expired(pfl->cmd);
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/* Reset flash */
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toggle_dq7(pfl);
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if (pfl->bypass) {
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pfl->wcycle = 2;
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} else {
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pflash_register_memory(pfl, 1);
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pfl->wcycle = 0;
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}
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pfl->cmd = 0;
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}
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static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr offset,
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int width, int be)
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{
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hwaddr boff;
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uint32_t ret;
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uint8_t *p;
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ret = -1;
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/* Lazy reset to ROMD mode after a certain amount of read accesses */
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if (!pfl->rom_mode && pfl->wcycle == 0 &&
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++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
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pflash_register_memory(pfl, 1);
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}
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offset &= pfl->chip_len - 1;
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boff = offset & 0xFF;
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if (pfl->width == 2)
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boff = boff >> 1;
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else if (pfl->width == 4)
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boff = boff >> 2;
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switch (pfl->cmd) {
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default:
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/* This should never happen : reset state & treat it as a read*/
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DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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pfl->wcycle = 0;
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pfl->cmd = 0;
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/* fall through to the read code */
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case 0x80:
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/* We accept reads during second unlock sequence... */
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case 0x00:
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flash_read:
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/* Flash area read */
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p = pfl->storage;
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switch (width) {
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case 1:
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ret = p[offset];
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break;
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case 2:
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if (be) {
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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} else {
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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}
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break;
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case 4:
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if (be) {
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16;
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ret |= p[offset + 2] << 8;
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ret |= p[offset + 3];
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} else {
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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ret |= p[offset + 2] << 16;
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ret |= p[offset + 3] << 24;
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}
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break;
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}
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trace_pflash_data_read(offset, width << 1, ret);
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break;
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case 0x90:
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/* flash ID read */
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switch (boff) {
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case 0x00:
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case 0x01:
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ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
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break;
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case 0x02:
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ret = 0x00; /* Pretend all sectors are unprotected */
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break;
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case 0x0E:
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case 0x0F:
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ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
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if (ret != (uint8_t)-1) {
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break;
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}
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/* Fall through to data read. */
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default:
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goto flash_read;
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}
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DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx32 "\n", __func__, boff, ret);
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break;
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case 0xA0:
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case 0x10:
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case 0x30:
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/* Status register read */
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ret = pfl->status;
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DPRINTF("%s: status %" PRIx32 "\n", __func__, ret);
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toggle_dq6(pfl);
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break;
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case 0x98:
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/* CFI query mode */
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if (boff < sizeof(pfl->cfi_table)) {
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ret = pfl->cfi_table[boff];
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} else {
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ret = 0;
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}
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break;
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}
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trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle);
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return ret;
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}
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/* update flash content on disk */
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static void pflash_update(PFlashCFI02 *pfl, int offset,
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int size)
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{
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int offset_end;
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if (pfl->blk) {
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offset_end = offset + size;
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/* widen to sector boundaries */
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offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
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offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
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blk_pwrite(pfl->blk, offset, pfl->storage + offset,
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offset_end - offset, 0);
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}
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}
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static void pflash_write(PFlashCFI02 *pfl, hwaddr offset,
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uint32_t value, int width, int be)
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{
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hwaddr boff;
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uint8_t *p;
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uint8_t cmd;
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trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle);
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cmd = value;
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if (pfl->cmd != 0xA0 && cmd == 0xF0) {
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goto reset_flash;
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}
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offset &= pfl->chip_len - 1;
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boff = offset & (pfl->sector_len - 1);
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if (pfl->width == 2)
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boff = boff >> 1;
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else if (pfl->width == 4)
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boff = boff >> 2;
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switch (pfl->wcycle) {
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case 0:
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/* Set the device in I/O access mode if required */
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if (pfl->rom_mode)
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pflash_register_memory(pfl, 0);
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pfl->read_counter = 0;
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/* We're in read mode */
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check_unlock0:
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if (boff == 0x55 && cmd == 0x98) {
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enter_CFI_mode:
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/* Enter CFI query mode */
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pfl->wcycle = WCYCLE_CFI;
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pfl->cmd = 0x98;
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return;
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}
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if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
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DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
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__func__, boff, cmd, pfl->unlock_addr0);
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goto reset_flash;
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}
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DPRINTF("%s: unlock sequence started\n", __func__);
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break;
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case 1:
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/* We started an unlock sequence */
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check_unlock1:
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if (boff != pfl->unlock_addr1 || cmd != 0x55) {
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DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
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boff, cmd);
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goto reset_flash;
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}
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DPRINTF("%s: unlock sequence done\n", __func__);
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break;
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case 2:
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/* We finished an unlock sequence */
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if (!pfl->bypass && boff != pfl->unlock_addr0) {
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DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
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boff, cmd);
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goto reset_flash;
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}
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switch (cmd) {
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case 0x20:
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pfl->bypass = 1;
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goto do_bypass;
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case 0x80:
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case 0x90:
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case 0xA0:
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pfl->cmd = cmd;
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DPRINTF("%s: starting command %02x\n", __func__, cmd);
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break;
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default:
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DPRINTF("%s: unknown command %02x\n", __func__, cmd);
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goto reset_flash;
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}
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break;
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case 3:
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switch (pfl->cmd) {
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case 0x80:
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/* We need another unlock sequence */
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goto check_unlock0;
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case 0xA0:
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trace_pflash_data_write(offset, width << 1, value, 0);
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if (!pfl->ro) {
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p = (uint8_t *)pfl->storage + offset;
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if (pfl->be) {
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uint64_t current = ldn_be_p(p, width);
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stn_be_p(p, width, current & value);
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} else {
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uint64_t current = ldn_le_p(p, width);
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stn_le_p(p, width, current & value);
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}
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pflash_update(pfl, offset, width);
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}
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/*
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* While programming, status bit DQ7 should hold the opposite
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* value from how it was programmed.
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*/
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set_dq7(pfl, ~value);
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/* Let's pretend write is immediate */
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if (pfl->bypass)
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goto do_bypass;
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goto reset_flash;
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case 0x90:
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if (pfl->bypass && cmd == 0x00) {
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/* Unlock bypass reset */
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goto reset_flash;
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}
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/* We can enter CFI query mode from autoselect mode */
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if (boff == 0x55 && cmd == 0x98)
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goto enter_CFI_mode;
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/* No break here */
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default:
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DPRINTF("%s: invalid write for command %02x\n",
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__func__, pfl->cmd);
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goto reset_flash;
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}
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case 4:
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switch (pfl->cmd) {
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case 0xA0:
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/* Ignore writes while flash data write is occurring */
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/* As we suppose write is immediate, this should never happen */
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return;
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case 0x80:
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goto check_unlock1;
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default:
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/* Should never happen */
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DPRINTF("%s: invalid command state %02x (wc 4)\n",
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__func__, pfl->cmd);
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goto reset_flash;
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}
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break;
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case 5:
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switch (cmd) {
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case 0x10:
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if (boff != pfl->unlock_addr0) {
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DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
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__func__, offset);
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goto reset_flash;
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}
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/* Chip erase */
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DPRINTF("%s: start chip erase\n", __func__);
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if (!pfl->ro) {
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memset(pfl->storage, 0xFF, pfl->chip_len);
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pflash_update(pfl, 0, pfl->chip_len);
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}
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set_dq7(pfl, 0x00);
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/* Let's wait 5 seconds before chip erase is done */
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timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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(NANOSECONDS_PER_SECOND * 5));
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break;
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case 0x30:
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/* Sector erase */
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p = pfl->storage;
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offset &= ~(pfl->sector_len - 1);
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DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__,
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offset);
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if (!pfl->ro) {
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memset(p + offset, 0xFF, pfl->sector_len);
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pflash_update(pfl, offset, pfl->sector_len);
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}
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set_dq7(pfl, 0x00);
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/* Let's wait 1/2 second before sector erase is done */
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timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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(NANOSECONDS_PER_SECOND / 2));
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break;
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default:
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DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
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goto reset_flash;
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}
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pfl->cmd = cmd;
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break;
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case 6:
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switch (pfl->cmd) {
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case 0x10:
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/* Ignore writes during chip erase */
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return;
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case 0x30:
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/* Ignore writes during sector erase */
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return;
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default:
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/* Should never happen */
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DPRINTF("%s: invalid command state %02x (wc 6)\n",
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__func__, pfl->cmd);
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goto reset_flash;
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}
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break;
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/* Special values for CFI queries */
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case WCYCLE_CFI:
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DPRINTF("%s: invalid write in CFI query mode\n", __func__);
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goto reset_flash;
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default:
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/* Should never happen */
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DPRINTF("%s: invalid write state (wc 7)\n", __func__);
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goto reset_flash;
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}
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pfl->wcycle++;
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return;
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/* Reset flash */
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reset_flash:
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trace_pflash_reset();
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pfl->bypass = 0;
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pfl->wcycle = 0;
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pfl->cmd = 0;
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return;
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do_bypass:
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pfl->wcycle = 2;
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pfl->cmd = 0;
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}
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static uint64_t pflash_be_readfn(void *opaque, hwaddr addr, unsigned size)
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{
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return pflash_read(opaque, addr, size, 1);
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}
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static void pflash_be_writefn(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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pflash_write(opaque, addr, value, size, 1);
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}
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static uint64_t pflash_le_readfn(void *opaque, hwaddr addr, unsigned size)
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{
|
|
return pflash_read(opaque, addr, size, 0);
|
|
}
|
|
|
|
static void pflash_le_writefn(void *opaque, hwaddr addr,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
pflash_write(opaque, addr, value, size, 0);
|
|
}
|
|
|
|
static const MemoryRegionOps pflash_cfi02_ops_be = {
|
|
.read = pflash_be_readfn,
|
|
.write = pflash_be_writefn,
|
|
.valid.min_access_size = 1,
|
|
.valid.max_access_size = 4,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static const MemoryRegionOps pflash_cfi02_ops_le = {
|
|
.read = pflash_le_readfn,
|
|
.write = pflash_le_writefn,
|
|
.valid.min_access_size = 1,
|
|
.valid.max_access_size = 4,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
PFlashCFI02 *pfl = PFLASH_CFI02(dev);
|
|
uint32_t chip_len;
|
|
int ret;
|
|
Error *local_err = NULL;
|
|
|
|
if (pfl->sector_len == 0) {
|
|
error_setg(errp, "attribute \"sector-length\" not specified or zero.");
|
|
return;
|
|
}
|
|
if (pfl->nb_blocs == 0) {
|
|
error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
|
|
return;
|
|
}
|
|
if (pfl->name == NULL) {
|
|
error_setg(errp, "attribute \"name\" not specified.");
|
|
return;
|
|
}
|
|
|
|
chip_len = pfl->sector_len * pfl->nb_blocs;
|
|
|
|
memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ?
|
|
&pflash_cfi02_ops_be : &pflash_cfi02_ops_le,
|
|
pfl, pfl->name, chip_len, &local_err);
|
|
if (local_err) {
|
|
error_propagate(errp, local_err);
|
|
return;
|
|
}
|
|
|
|
pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
|
|
pfl->chip_len = chip_len;
|
|
|
|
if (pfl->blk) {
|
|
uint64_t perm;
|
|
pfl->ro = blk_is_read_only(pfl->blk);
|
|
perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
|
|
ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
|
|
if (ret < 0) {
|
|
return;
|
|
}
|
|
} else {
|
|
pfl->ro = 0;
|
|
}
|
|
|
|
if (pfl->blk) {
|
|
if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, chip_len,
|
|
errp)) {
|
|
vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
|
|
return;
|
|
}
|
|
}
|
|
|
|
pflash_setup_mappings(pfl);
|
|
pfl->rom_mode = 1;
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
|
|
|
|
timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
|
|
pfl->wcycle = 0;
|
|
pfl->cmd = 0;
|
|
pfl->status = 0;
|
|
/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
|
/* Standard "QRY" string */
|
|
pfl->cfi_table[0x10] = 'Q';
|
|
pfl->cfi_table[0x11] = 'R';
|
|
pfl->cfi_table[0x12] = 'Y';
|
|
/* Command set (AMD/Fujitsu) */
|
|
pfl->cfi_table[0x13] = 0x02;
|
|
pfl->cfi_table[0x14] = 0x00;
|
|
/* Primary extended table address */
|
|
pfl->cfi_table[0x15] = 0x31;
|
|
pfl->cfi_table[0x16] = 0x00;
|
|
/* Alternate command set (none) */
|
|
pfl->cfi_table[0x17] = 0x00;
|
|
pfl->cfi_table[0x18] = 0x00;
|
|
/* Alternate extended table (none) */
|
|
pfl->cfi_table[0x19] = 0x00;
|
|
pfl->cfi_table[0x1A] = 0x00;
|
|
/* Vcc min */
|
|
pfl->cfi_table[0x1B] = 0x27;
|
|
/* Vcc max */
|
|
pfl->cfi_table[0x1C] = 0x36;
|
|
/* Vpp min (no Vpp pin) */
|
|
pfl->cfi_table[0x1D] = 0x00;
|
|
/* Vpp max (no Vpp pin) */
|
|
pfl->cfi_table[0x1E] = 0x00;
|
|
/* Reserved */
|
|
pfl->cfi_table[0x1F] = 0x07;
|
|
/* Timeout for min size buffer write (NA) */
|
|
pfl->cfi_table[0x20] = 0x00;
|
|
/* Typical timeout for block erase (512 ms) */
|
|
pfl->cfi_table[0x21] = 0x09;
|
|
/* Typical timeout for full chip erase (4096 ms) */
|
|
pfl->cfi_table[0x22] = 0x0C;
|
|
/* Reserved */
|
|
pfl->cfi_table[0x23] = 0x01;
|
|
/* Max timeout for buffer write (NA) */
|
|
pfl->cfi_table[0x24] = 0x00;
|
|
/* Max timeout for block erase */
|
|
pfl->cfi_table[0x25] = 0x0A;
|
|
/* Max timeout for chip erase */
|
|
pfl->cfi_table[0x26] = 0x0D;
|
|
/* Device size */
|
|
pfl->cfi_table[0x27] = ctz32(chip_len);
|
|
/* Flash device interface (8 & 16 bits) */
|
|
pfl->cfi_table[0x28] = 0x02;
|
|
pfl->cfi_table[0x29] = 0x00;
|
|
/* Max number of bytes in multi-bytes write */
|
|
/* XXX: disable buffered write as it's not supported */
|
|
// pfl->cfi_table[0x2A] = 0x05;
|
|
pfl->cfi_table[0x2A] = 0x00;
|
|
pfl->cfi_table[0x2B] = 0x00;
|
|
/* Number of erase block regions (uniform) */
|
|
pfl->cfi_table[0x2C] = 0x01;
|
|
/* Erase block region 1 */
|
|
pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
|
|
pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
|
|
pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
|
|
pfl->cfi_table[0x30] = pfl->sector_len >> 16;
|
|
|
|
/* Extended */
|
|
pfl->cfi_table[0x31] = 'P';
|
|
pfl->cfi_table[0x32] = 'R';
|
|
pfl->cfi_table[0x33] = 'I';
|
|
|
|
pfl->cfi_table[0x34] = '1';
|
|
pfl->cfi_table[0x35] = '0';
|
|
|
|
pfl->cfi_table[0x36] = 0x00;
|
|
pfl->cfi_table[0x37] = 0x00;
|
|
pfl->cfi_table[0x38] = 0x00;
|
|
pfl->cfi_table[0x39] = 0x00;
|
|
|
|
pfl->cfi_table[0x3a] = 0x00;
|
|
|
|
pfl->cfi_table[0x3b] = 0x00;
|
|
pfl->cfi_table[0x3c] = 0x00;
|
|
}
|
|
|
|
static Property pflash_cfi02_properties[] = {
|
|
DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk),
|
|
DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, nb_blocs, 0),
|
|
DEFINE_PROP_UINT32("sector-length", PFlashCFI02, sector_len, 0),
|
|
DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0),
|
|
DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0),
|
|
DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0),
|
|
DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0),
|
|
DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0),
|
|
DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0),
|
|
DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0),
|
|
DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0),
|
|
DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0),
|
|
DEFINE_PROP_STRING("name", PFlashCFI02, name),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp)
|
|
{
|
|
PFlashCFI02 *pfl = PFLASH_CFI02(dev);
|
|
timer_del(&pfl->timer);
|
|
}
|
|
|
|
static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pflash_cfi02_realize;
|
|
dc->unrealize = pflash_cfi02_unrealize;
|
|
dc->props = pflash_cfi02_properties;
|
|
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pflash_cfi02_info = {
|
|
.name = TYPE_PFLASH_CFI02,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(PFlashCFI02),
|
|
.class_init = pflash_cfi02_class_init,
|
|
};
|
|
|
|
static void pflash_cfi02_register_types(void)
|
|
{
|
|
type_register_static(&pflash_cfi02_info);
|
|
}
|
|
|
|
type_init(pflash_cfi02_register_types)
|
|
|
|
PFlashCFI02 *pflash_cfi02_register(hwaddr base,
|
|
const char *name,
|
|
hwaddr size,
|
|
BlockBackend *blk,
|
|
uint32_t sector_len,
|
|
int nb_mappings, int width,
|
|
uint16_t id0, uint16_t id1,
|
|
uint16_t id2, uint16_t id3,
|
|
uint16_t unlock_addr0,
|
|
uint16_t unlock_addr1,
|
|
int be)
|
|
{
|
|
DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02);
|
|
|
|
if (blk) {
|
|
qdev_prop_set_drive(dev, "drive", blk, &error_abort);
|
|
}
|
|
assert(size % sector_len == 0);
|
|
qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
|
|
qdev_prop_set_uint32(dev, "sector-length", sector_len);
|
|
qdev_prop_set_uint8(dev, "width", width);
|
|
qdev_prop_set_uint8(dev, "mappings", nb_mappings);
|
|
qdev_prop_set_uint8(dev, "big-endian", !!be);
|
|
qdev_prop_set_uint16(dev, "id0", id0);
|
|
qdev_prop_set_uint16(dev, "id1", id1);
|
|
qdev_prop_set_uint16(dev, "id2", id2);
|
|
qdev_prop_set_uint16(dev, "id3", id3);
|
|
qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
|
|
qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
|
|
qdev_prop_set_string(dev, "name", name);
|
|
qdev_init_nofail(dev);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
|
|
return PFLASH_CFI02(dev);
|
|
}
|