Yang Weijiang c3c67679f6 target/i386: Support Arch LBR in CPUID enumeration ...

If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, the processor
supports Architectural LBRs. In this case, CPUID leaf 01CH
indicates details of the Architectural LBRs capabilities.
XSAVE support for Architectural LBRs is enumerated in
CPUID.(EAX=0DH, ECX=0FH).

Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-9-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

2022-05-14 12:32:41 +02:00

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hax

Clean up header guards that don't match their file name

2022-05-11 16:49:06 +02:00

hvf

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kvm

target/i386: Add MSR access interface for Arch LBR

2022-05-14 12:32:41 +02:00

nvmm

Clean up header guards that don't match their file name

2022-05-11 16:49:06 +02:00

tcg

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whpx

WHPX: fixed TPR/CR8 translation issues affecting VM debugging

2022-05-14 12:32:40 +02:00

arch_dump.c

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arch_memory_mapping.c

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cpu-dump.c

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cpu-internal.h

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cpu-param.h

Normalize header guard symbol definition

2022-05-11 16:50:26 +02:00

cpu-qom.h

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cpu-sysemu.c

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cpu.c

target/i386: Support Arch LBR in CPUID enumeration

2022-05-14 12:32:41 +02:00

cpu.h

target/i386: Add MSR access interface for Arch LBR

2022-05-14 12:32:41 +02:00

gdbstub.c

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helper.c

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helper.h

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host-cpu.c

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host-cpu.h

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Kconfig

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machine.c

target/i386: Enable Arch LBR migration states in vmstate

2022-05-14 12:32:41 +02:00

meson.build

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monitor.c

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ops_sse_header.h

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ops_sse.h

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sev-sysemu-stub.c

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sev.c

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sev.h

Clean up header guards that don't match their file name

2022-05-11 16:49:06 +02:00

shift_helper_template.h

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svm.h

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trace-events

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trace.h

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xsave_helper.c

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