c397a2d3e4
PCI interrupt wiring and device creation were performed in create() functions which are obsolete. Move these tasks into QOM functions to modernize the code. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220603185045.143789-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
341 lines
9.5 KiB
C
341 lines
9.5 KiB
C
/*
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* QEMU PIIX4 PCI Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2018 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "hw/southbridge/piix.h"
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#include "hw/pci/pci.h"
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#include "hw/isa/isa.h"
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#include "hw/intc/i8259.h"
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#include "hw/dma/i8257.h"
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#include "hw/timer/i8254.h"
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#include "hw/rtc/mc146818rtc.h"
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#include "hw/ide/pci.h"
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#include "hw/acpi/piix4.h"
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#include "hw/usb/hcd-uhci.h"
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#include "migration/vmstate.h"
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#include "sysemu/reset.h"
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#include "sysemu/runstate.h"
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#include "qom/object.h"
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struct PIIX4State {
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PCIDevice dev;
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qemu_irq cpu_intr;
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qemu_irq *isa;
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RTCState rtc;
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PCIIDEState ide;
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UHCIState uhci;
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/* Reset Control Register */
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MemoryRegion rcr_mem;
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uint8_t rcr;
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};
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OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
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static void piix4_set_irq(void *opaque, int irq_num, int level)
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{
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int i, pic_irq, pic_level;
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PIIX4State *s = opaque;
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PCIBus *bus = pci_get_bus(&s->dev);
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/* now we change the pic irq level according to the piix irq mappings */
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/* XXX: optimize */
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pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
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if (pic_irq < ISA_NUM_IRQS) {
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/* The pic level is the logical OR of all the PCI irqs mapped to it. */
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pic_level = 0;
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for (i = 0; i < PIIX_NUM_PIRQS; i++) {
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if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
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pic_level |= pci_bus_get_irq_level(bus, i);
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}
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}
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qemu_set_irq(s->isa[pic_irq], pic_level);
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}
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}
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static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
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{
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int slot;
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slot = PCI_SLOT(pci_dev->devfn);
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switch (slot) {
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/* PIIX4 USB */
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case 10:
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return 3;
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/* AMD 79C973 Ethernet */
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case 11:
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return 1;
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/* Crystal 4281 Sound */
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case 12:
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return 2;
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/* PCI slot 1 to 4 */
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case 18 ... 21:
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return ((slot - 18) + irq_num) & 0x03;
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/* Unknown device, don't do any translation */
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default:
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return irq_num;
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}
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}
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static void piix4_isa_reset(DeviceState *dev)
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{
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PIIX4State *d = PIIX4_PCI_DEVICE(dev);
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uint8_t *pci_conf = d->dev.config;
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pci_conf[0x04] = 0x07; // master, memory and I/O
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pci_conf[0x05] = 0x00;
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pci_conf[0x06] = 0x00;
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pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
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pci_conf[0x4c] = 0x4d;
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pci_conf[0x4e] = 0x03;
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pci_conf[0x4f] = 0x00;
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pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
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pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
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pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
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pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
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pci_conf[0x69] = 0x02;
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pci_conf[0x70] = 0x80;
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pci_conf[0x76] = 0x0c;
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pci_conf[0x77] = 0x0c;
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pci_conf[0x78] = 0x02;
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pci_conf[0x79] = 0x00;
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pci_conf[0x80] = 0x00;
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pci_conf[0x82] = 0x00;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa2] = 0x00;
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pci_conf[0xa3] = 0x00;
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pci_conf[0xa4] = 0x00;
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pci_conf[0xa5] = 0x00;
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pci_conf[0xa6] = 0x00;
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pci_conf[0xa7] = 0x00;
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pci_conf[0xa8] = 0x0f;
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pci_conf[0xaa] = 0x00;
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pci_conf[0xab] = 0x00;
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pci_conf[0xac] = 0x00;
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pci_conf[0xae] = 0x00;
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}
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static int piix4_ide_post_load(void *opaque, int version_id)
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{
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PIIX4State *s = opaque;
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if (version_id == 2) {
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s->rcr = 0;
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}
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return 0;
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}
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static const VMStateDescription vmstate_piix4 = {
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.name = "PIIX4",
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.version_id = 3,
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.minimum_version_id = 2,
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.post_load = piix4_ide_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, PIIX4State),
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VMSTATE_UINT8_V(rcr, PIIX4State, 3),
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VMSTATE_END_OF_LIST()
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}
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};
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static void piix4_request_i8259_irq(void *opaque, int irq, int level)
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{
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PIIX4State *s = opaque;
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qemu_set_irq(s->cpu_intr, level);
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}
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static void piix4_set_i8259_irq(void *opaque, int irq, int level)
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{
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PIIX4State *s = opaque;
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qemu_set_irq(s->isa[irq], level);
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}
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static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int len)
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{
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PIIX4State *s = opaque;
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if (val & 4) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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return;
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}
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s->rcr = val & 2; /* keep System Reset type only */
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}
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static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
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{
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PIIX4State *s = opaque;
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return s->rcr;
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}
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static const MemoryRegionOps piix4_rcr_ops = {
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.read = piix4_rcr_read,
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.write = piix4_rcr_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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static void piix4_realize(PCIDevice *dev, Error **errp)
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{
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PIIX4State *s = PIIX4_PCI_DEVICE(dev);
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PCIBus *pci_bus = pci_get_bus(dev);
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ISABus *isa_bus;
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qemu_irq *i8259_out_irq;
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isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
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pci_address_space_io(dev), errp);
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if (!isa_bus) {
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return;
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}
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qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
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"isa", ISA_NUM_IRQS);
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qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
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"intr", 1);
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memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
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"reset-control", 1);
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memory_region_add_subregion_overlap(pci_address_space_io(dev),
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PIIX_RCR_IOPORT, &s->rcr_mem, 1);
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/* initialize i8259 pic */
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i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
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s->isa = i8259_init(isa_bus, *i8259_out_irq);
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/* initialize ISA irqs */
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isa_bus_irqs(isa_bus, s->isa);
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/* initialize pit */
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i8254_pit_init(isa_bus, 0x40, 0, NULL);
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/* DMA */
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i8257_dma_init(isa_bus, 0);
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/* RTC */
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qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
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if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
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return;
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}
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s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
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/* IDE */
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qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1);
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if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
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return;
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}
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pci_ide_create_devs(PCI_DEVICE(&s->ide));
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/* USB */
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qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2);
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if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) {
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return;
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}
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pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
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}
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static void piix4_init(Object *obj)
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{
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PIIX4State *s = PIIX4_PCI_DEVICE(obj);
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object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
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object_initialize_child(obj, "ide", &s->ide, "piix4-ide");
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object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci");
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}
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static void piix4_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = piix4_realize;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
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k->class_id = PCI_CLASS_BRIDGE_ISA;
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dc->reset = piix4_isa_reset;
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dc->desc = "ISA bridge";
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dc->vmsd = &vmstate_piix4;
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/*
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* Reason: part of PIIX4 southbridge, needs to be wired up,
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* e.g. by mips_malta_init()
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*/
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dc->user_creatable = false;
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dc->hotpluggable = false;
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}
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static const TypeInfo piix4_info = {
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.name = TYPE_PIIX4_PCI_DEVICE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PIIX4State),
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.instance_init = piix4_init,
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.class_init = piix4_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void piix4_register_types(void)
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{
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type_register_static(&piix4_info);
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}
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type_init(piix4_register_types)
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DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
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{
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PCIDevice *pci;
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DeviceState *dev;
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int devfn = PCI_DEVFN(10, 0);
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pci = pci_create_simple_multifunction(pci_bus, devfn, true,
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TYPE_PIIX4_PCI_DEVICE);
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dev = DEVICE(pci);
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if (isa_bus) {
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*isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
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}
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if (smbus) {
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pci = pci_new(devfn + 3, TYPE_PIIX4_PM);
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qdev_prop_set_uint32(DEVICE(pci), "smb_io_base", 0x1100);
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qdev_prop_set_bit(DEVICE(pci), "smm-enabled", 0);
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pci_realize_and_unref(pci, pci_bus, &error_fatal);
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qdev_connect_gpio_out(DEVICE(pci), 0,
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qdev_get_gpio_in_named(dev, "isa", 9));
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*smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pci), "i2c"));
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}
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return dev;
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}
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