9ae6ecd848
Mark the shakti_c machine as not user creatable. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <c617a04d4e3dd041a3427b47a1b1d5ab475a2edd.1632871759.git.alistair.francis@wdc.com>
193 lines
6.7 KiB
C
193 lines
6.7 KiB
C
/*
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* Shakti C-class SoC emulation
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*
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* Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/boards.h"
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#include "hw/riscv/shakti_c.h"
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#include "qapi/error.h"
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#include "hw/intc/sifive_plic.h"
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#include "hw/intc/riscv_aclint.h"
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#include "sysemu/sysemu.h"
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#include "hw/qdev-properties.h"
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#include "exec/address-spaces.h"
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#include "hw/riscv/boot.h"
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} shakti_c_memmap[] = {
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[SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
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[SHAKTI_C_RAM] = { 0x80000000, 0x0 },
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[SHAKTI_C_UART] = { 0x00011300, 0x00040 },
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[SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
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[SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
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[SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
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[SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
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};
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static void shakti_c_machine_state_init(MachineState *mstate)
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{
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ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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/* Allow only Shakti C CPU for this platform */
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if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
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error_report("This board can only be used with Shakti C CPU");
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exit(1);
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}
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/* Initialize SoC */
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object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
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TYPE_RISCV_SHAKTI_SOC);
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qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
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/* register RAM */
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memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
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mstate->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory,
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shakti_c_memmap[SHAKTI_C_RAM].base,
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main_mem);
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/* ROM reset vector */
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riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
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shakti_c_memmap[SHAKTI_C_RAM].base,
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shakti_c_memmap[SHAKTI_C_ROM].base,
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shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0,
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NULL);
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if (mstate->firmware) {
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riscv_load_firmware(mstate->firmware,
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shakti_c_memmap[SHAKTI_C_RAM].base,
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NULL);
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}
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}
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static void shakti_c_machine_instance_init(Object *obj)
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{
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}
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static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(klass);
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mc->desc = "RISC-V Board compatible with Shakti SDK";
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mc->init = shakti_c_machine_state_init;
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mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
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}
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static const TypeInfo shakti_c_machine_type_info = {
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.name = TYPE_RISCV_SHAKTI_MACHINE,
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.parent = TYPE_MACHINE,
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.class_init = shakti_c_machine_class_init,
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.instance_init = shakti_c_machine_instance_init,
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.instance_size = sizeof(ShaktiCMachineState),
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};
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static void shakti_c_machine_type_info_register(void)
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{
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type_register_static(&shakti_c_machine_type_info);
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}
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type_init(shakti_c_machine_type_info_register)
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static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
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MemoryRegion *system_memory = get_system_memory();
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sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
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sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
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(char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0,
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SHAKTI_C_PLIC_NUM_SOURCES,
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SHAKTI_C_PLIC_NUM_PRIORITIES,
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SHAKTI_C_PLIC_PRIORITY_BASE,
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SHAKTI_C_PLIC_PENDING_BASE,
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SHAKTI_C_PLIC_ENABLE_BASE,
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SHAKTI_C_PLIC_ENABLE_STRIDE,
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SHAKTI_C_PLIC_CONTEXT_BASE,
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SHAKTI_C_PLIC_CONTEXT_STRIDE,
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shakti_c_memmap[SHAKTI_C_PLIC].size);
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riscv_aclint_swi_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
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0, 1, false);
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riscv_aclint_mtimer_create(shakti_c_memmap[SHAKTI_C_CLINT].base +
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RISCV_ACLINT_SWI_SIZE,
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RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, 1,
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RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
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RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
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qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
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if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
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shakti_c_memmap[SHAKTI_C_UART].base);
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/* ROM */
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memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
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shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
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memory_region_add_subregion(system_memory,
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shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
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}
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static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = shakti_c_soc_state_realize;
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/*
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* Reasons:
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* - Creates CPUS in riscv_hart_realize(), and can create unintended
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* CPUs
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* - Uses serial_hds in realize function, thus can't be used twice
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*/
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dc->user_creatable = false;
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}
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static void shakti_c_soc_instance_init(Object *obj)
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{
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ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
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object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
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object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
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/*
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* CPU type is fixed and we are not supporting passing from commandline yet.
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* So let it be in instance_init. When supported should use ms->cpu_type
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* instead of TYPE_RISCV_CPU_SHAKTI_C
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*/
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object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
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TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
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object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
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&error_abort);
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}
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static const TypeInfo shakti_c_type_info = {
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.name = TYPE_RISCV_SHAKTI_SOC,
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.parent = TYPE_DEVICE,
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.class_init = shakti_c_soc_class_init,
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.instance_init = shakti_c_soc_instance_init,
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.instance_size = sizeof(ShaktiCSoCState),
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};
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static void shakti_c_type_info_register(void)
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{
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type_register_static(&shakti_c_type_info);
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}
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type_init(shakti_c_type_info_register)
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