60efd4297d
Replace template patching and runtime calculation in _CRS() method with static _CRS defined in SSDT. No functional change except of as mentined above and _CRS being moved from DSDT to SSDT. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
437 lines
15 KiB
Plaintext
437 lines
15 KiB
Plaintext
/*
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* Bochs/QEMU ACPI DSDT ASL definition
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Copyright (c) 2010 Isaku Yamahata
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* yamahata at valinux co jp
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* Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
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*/
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ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode
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DefinitionBlock (
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"q35-acpi-dsdt.aml",// Output Filename
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"DSDT", // Signature
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0x01, // DSDT Compliance Revision
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"BXPC", // OEMID
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"BXDSDT", // TABLE ID
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0x2 // OEM Revision
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)
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{
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#include "acpi-dsdt-dbug.dsl"
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Scope(\_SB) {
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OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
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OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
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Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
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PCIB, 8,
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}
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}
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/****************************************************************
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* PCI Bus definition
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****************************************************************/
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Scope(\_SB) {
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Device(PCI0) {
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Name(_HID, EisaId("PNP0A08"))
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Name(_CID, EisaId("PNP0A03"))
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Name(_ADR, 0x00)
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Name(_UID, 1)
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External(ISA, DeviceObj)
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// _OSC: based on sample of ACPI3.0b spec
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Name(SUPP, 0) // PCI _OSC Support Field value
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Name(CTRL, 0) // PCI _OSC Control Field value
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Method(_OSC, 4) {
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// Create DWORD-addressable fields from the Capabilities Buffer
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CreateDWordField(Arg3, 0, CDW1)
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// Check for proper UUID
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If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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// Create DWORD-addressable fields from the Capabilities Buffer
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CreateDWordField(Arg3, 4, CDW2)
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CreateDWordField(Arg3, 8, CDW3)
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// Save Capabilities DWORD2 & 3
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Store(CDW2, SUPP)
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Store(CDW3, CTRL)
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// Always allow native PME, AER (no dependencies)
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// Never allow SHPC (no SHPC controller in this system)
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And(CTRL, 0x1D, CTRL)
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#if 0 // For now, nothing to do
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If (Not(And(CDW1, 1))) { // Query flag clear?
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// Disable GPEs for features granted native control.
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If (And(CTRL, 0x01)) { // Hot plug control granted?
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Store(0, HPCE) // clear the hot plug SCI enable bit
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Store(1, HPCS) // clear the hot plug SCI status bit
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}
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If (And(CTRL, 0x04)) { // PME control granted?
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Store(0, PMCE) // clear the PME SCI enable bit
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Store(1, PMCS) // clear the PME SCI status bit
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}
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If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
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// Set status to not restore PCI Express cap structure
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// upon resume from S3
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Store(1, S3CR)
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}
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}
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#endif
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If (LNotEqual(Arg1, One)) {
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// Unknown revision
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Or(CDW1, 0x08, CDW1)
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}
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If (LNotEqual(CDW3, CTRL)) {
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// Capabilities bits were masked
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Or(CDW1, 0x10, CDW1)
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}
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// Update DWORD3 in the buffer
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Store(CTRL, CDW3)
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} Else {
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Or(CDW1, 4, CDW1) // Unrecognized UUID
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}
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Return (Arg3)
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}
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}
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}
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#include "acpi-dsdt-hpet.dsl"
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/****************************************************************
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* LPC ISA bridge
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****************************************************************/
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Scope(\_SB.PCI0) {
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/* PCI D31:f0 LPC ISA bridge */
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Device(ISA) {
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Name (_ADR, 0x001F0000) // _ADR: Address
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/* ICH9 PCI to ISA irq remapping */
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OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
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OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
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Field(LPCD, AnyAcc, NoLock, Preserve) {
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COMA, 3,
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, 1,
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COMB, 3,
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Offset(0x01),
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LPTD, 2,
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, 2,
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FDCD, 2
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}
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OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
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Field(LPCE, AnyAcc, NoLock, Preserve) {
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CAEN, 1,
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CBEN, 1,
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LPEN, 1,
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FDEN, 1
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}
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}
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}
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#define DSDT_APPLESMC_STA q35_dsdt_applesmc_sta
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#include "acpi-dsdt-isa.dsl"
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/****************************************************************
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* PCI IRQs
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****************************************************************/
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/* Zero => PIC mode, One => APIC Mode */
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Name(\PICF, Zero)
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Method(\_PIC, 1, NotSerialized) {
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Store(Arg0, \PICF)
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}
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Scope(\_SB) {
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Scope(PCI0) {
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#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
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Package() { nr##ffff, 0, lnk0, 0 }, \
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Package() { nr##ffff, 1, lnk1, 0 }, \
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Package() { nr##ffff, 2, lnk2, 0 }, \
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Package() { nr##ffff, 3, lnk3, 0 }
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#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
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#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
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#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
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#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
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#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
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#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
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#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
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#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
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Name(PRTP, package() {
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prt_slot_lnkE(0x0000),
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prt_slot_lnkF(0x0001),
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prt_slot_lnkG(0x0002),
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prt_slot_lnkH(0x0003),
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prt_slot_lnkE(0x0004),
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prt_slot_lnkF(0x0005),
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prt_slot_lnkG(0x0006),
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prt_slot_lnkH(0x0007),
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prt_slot_lnkE(0x0008),
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prt_slot_lnkF(0x0009),
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prt_slot_lnkG(0x000a),
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prt_slot_lnkH(0x000b),
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prt_slot_lnkE(0x000c),
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prt_slot_lnkF(0x000d),
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prt_slot_lnkG(0x000e),
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prt_slot_lnkH(0x000f),
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prt_slot_lnkE(0x0010),
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prt_slot_lnkF(0x0011),
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prt_slot_lnkG(0x0012),
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prt_slot_lnkH(0x0013),
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prt_slot_lnkE(0x0014),
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prt_slot_lnkF(0x0015),
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prt_slot_lnkG(0x0016),
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prt_slot_lnkH(0x0017),
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prt_slot_lnkE(0x0018),
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/* INTA -> PIRQA for slot 25 - 31
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see the default value of D<N>IR */
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prt_slot_lnkA(0x0019),
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prt_slot_lnkA(0x001a),
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prt_slot_lnkA(0x001b),
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prt_slot_lnkA(0x001c),
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prt_slot_lnkA(0x001d),
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/* PCIe->PCI bridge. use PIRQ[E-H] */
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prt_slot_lnkE(0x001e),
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prt_slot_lnkA(0x001f)
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})
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#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
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Package() { nr##ffff, 0, gsi0, 0 }, \
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Package() { nr##ffff, 1, gsi1, 0 }, \
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Package() { nr##ffff, 2, gsi2, 0 }, \
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Package() { nr##ffff, 3, gsi3, 0 }
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#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
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#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
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#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
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#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
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#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
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#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
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#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
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#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
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Name(PRTA, package() {
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prt_slot_gsiE(0x0000),
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prt_slot_gsiF(0x0001),
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prt_slot_gsiG(0x0002),
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prt_slot_gsiH(0x0003),
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prt_slot_gsiE(0x0004),
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prt_slot_gsiF(0x0005),
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prt_slot_gsiG(0x0006),
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prt_slot_gsiH(0x0007),
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prt_slot_gsiE(0x0008),
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prt_slot_gsiF(0x0009),
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prt_slot_gsiG(0x000a),
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prt_slot_gsiH(0x000b),
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prt_slot_gsiE(0x000c),
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prt_slot_gsiF(0x000d),
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prt_slot_gsiG(0x000e),
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prt_slot_gsiH(0x000f),
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prt_slot_gsiE(0x0010),
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prt_slot_gsiF(0x0011),
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prt_slot_gsiG(0x0012),
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prt_slot_gsiH(0x0013),
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prt_slot_gsiE(0x0014),
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prt_slot_gsiF(0x0015),
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prt_slot_gsiG(0x0016),
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prt_slot_gsiH(0x0017),
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prt_slot_gsiE(0x0018),
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/* INTA -> PIRQA for slot 25 - 31, but 30
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see the default value of D<N>IR */
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prt_slot_gsiA(0x0019),
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prt_slot_gsiA(0x001a),
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prt_slot_gsiA(0x001b),
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prt_slot_gsiA(0x001c),
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prt_slot_gsiA(0x001d),
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/* PCIe->PCI bridge. use PIRQ[E-H] */
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prt_slot_gsiE(0x001e),
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prt_slot_gsiA(0x001f)
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})
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Method(_PRT, 0, NotSerialized) {
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/* PCI IRQ routing table, example from ACPI 2.0a specification,
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section 6.2.8.1 */
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/* Note: we provide the same info as the PCI routing
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table of the Bochs BIOS */
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If (LEqual(\PICF, Zero)) {
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Return (PRTP)
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} Else {
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Return (PRTA)
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}
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}
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}
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Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
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PRQA, 8,
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PRQB, 8,
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PRQC, 8,
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PRQD, 8,
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Offset(0x08),
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PRQE, 8,
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PRQF, 8,
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PRQG, 8,
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PRQH, 8
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}
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Method(IQST, 1, NotSerialized) {
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// _STA method - get status
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If (And(0x80, Arg0)) {
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Return (0x09)
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}
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Return (0x0B)
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}
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Method(IQCR, 1, Serialized) {
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// _CRS method - get current settings
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Name(PRR0, ResourceTemplate() {
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Interrupt(, Level, ActiveHigh, Shared) { 0 }
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})
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CreateDWordField(PRR0, 0x05, PRRI)
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Store(And(Arg0, 0x0F), PRRI)
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Return (PRR0)
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}
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#define define_link(link, uid, reg) \
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Device(link) { \
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Name(_HID, EISAID("PNP0C0F")) \
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Name(_UID, uid) \
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Name(_PRS, ResourceTemplate() { \
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Interrupt(, Level, ActiveHigh, Shared) { \
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5, 10, 11 \
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} \
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}) \
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Method(_STA, 0, NotSerialized) { \
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Return (IQST(reg)) \
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} \
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Method(_DIS, 0, NotSerialized) { \
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Or(reg, 0x80, reg) \
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} \
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Method(_CRS, 0, NotSerialized) { \
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Return (IQCR(reg)) \
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} \
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Method(_SRS, 1, NotSerialized) { \
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CreateDWordField(Arg0, 0x05, PRRI) \
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Store(PRRI, reg) \
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} \
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}
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define_link(LNKA, 0, PRQA)
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define_link(LNKB, 1, PRQB)
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define_link(LNKC, 2, PRQC)
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define_link(LNKD, 3, PRQD)
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define_link(LNKE, 4, PRQE)
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define_link(LNKF, 5, PRQF)
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define_link(LNKG, 6, PRQG)
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define_link(LNKH, 7, PRQH)
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#define define_gsi_link(link, uid, gsi) \
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Device(link) { \
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Name(_HID, EISAID("PNP0C0F")) \
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Name(_UID, uid) \
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Name(_PRS, ResourceTemplate() { \
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Interrupt(, Level, ActiveHigh, Shared) { \
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gsi \
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} \
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}) \
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Name(_CRS, ResourceTemplate() { \
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Interrupt(, Level, ActiveHigh, Shared) { \
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gsi \
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} \
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}) \
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Method(_SRS, 1, NotSerialized) { \
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} \
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}
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define_gsi_link(GSIA, 0, 0x10)
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define_gsi_link(GSIB, 0, 0x11)
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define_gsi_link(GSIC, 0, 0x12)
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define_gsi_link(GSID, 0, 0x13)
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define_gsi_link(GSIE, 0, 0x14)
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define_gsi_link(GSIF, 0, 0x15)
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define_gsi_link(GSIG, 0, 0x16)
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define_gsi_link(GSIH, 0, 0x17)
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}
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#include "hw/acpi/pc-hotplug.h"
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#define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE
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#include "acpi-dsdt-cpu-hotplug.dsl"
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#include "acpi-dsdt-mem-hotplug.dsl"
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/****************************************************************
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* General purpose events
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****************************************************************/
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Scope(\_GPE) {
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Name(_HID, "ACPI0006")
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Method(_L00) {
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}
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Method(_L01) {
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}
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Method(_E02) {
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// CPU hotplug event
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\_SB.PRSC()
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}
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Method(_E03) {
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// Memory hotplug event
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\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_SCAN_METHOD()
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}
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Method(_L04) {
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}
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Method(_L05) {
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}
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Method(_L06) {
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}
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Method(_L07) {
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}
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Method(_L08) {
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}
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Method(_L09) {
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}
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Method(_L0A) {
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}
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Method(_L0B) {
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}
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Method(_L0C) {
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}
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Method(_L0D) {
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}
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Method(_L0E) {
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}
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Method(_L0F) {
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}
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}
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}
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