a31768c019
Extend comparison results from mask registers to SEW-width elements, following recommendations in The RISC-V SPEC Volume I (Version 20240411). This aligns with TCG's cmp_vec behavior by expanding compare results to full element width: all 1s for true, all 0s for false. Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241007025700.47259-7-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
25 lines
566 B
C
25 lines
566 B
C
/* SPDX-License-Identifier: MIT */
|
|
/*
|
|
* Define RISC-V target-specific operand constraints.
|
|
* Copyright (c) 2021 Linaro
|
|
*/
|
|
|
|
/*
|
|
* Define constraint letters for register sets:
|
|
* REGS(letter, register_mask)
|
|
*/
|
|
REGS('r', ALL_GENERAL_REGS)
|
|
REGS('v', ALL_VECTOR_REGS)
|
|
|
|
/*
|
|
* Define constraint letters for constants:
|
|
* CONST(letter, TCG_CT_CONST_* bit set)
|
|
*/
|
|
CONST('I', TCG_CT_CONST_S12)
|
|
CONST('J', TCG_CT_CONST_J12)
|
|
CONST('K', TCG_CT_CONST_S5)
|
|
CONST('L', TCG_CT_CONST_CMP_VI)
|
|
CONST('N', TCG_CT_CONST_N12)
|
|
CONST('M', TCG_CT_CONST_M12)
|
|
CONST('Z', TCG_CT_CONST_ZERO)
|