c1d66d378c
Somewhere in the history of time, the initialisation of the PCI buses for the AGP and PCI host bridges got mixed up in that the PCI host bridge was creating an instance of the AGP PCI bus, and the AGP PCI bus was missing. Swap the PCI host bridge over to use the correct PCI bus (including setting the kMacRISCPCIAddressSelect register used by MacOS X) and add the missing reference to the AGP PCI bus. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
555 lines
17 KiB
C
555 lines
17 KiB
C
/*
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* QEMU Uninorth PCI host (for all Mac99 and newer machines)
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/ppc/mac.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci-host/uninorth.h"
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#include "trace.h"
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static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
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static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (irq_num + (pci_dev->devfn >> 3)) & 3;
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}
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static void pci_unin_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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trace_unin_set_irq(unin_irq_line[irq_num], level);
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qemu_set_irq(pic[unin_irq_line[irq_num]], level);
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}
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static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
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{
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uint32_t retval;
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if (reg & (1u << 31)) {
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/* XXX OpenBIOS compatibility hack */
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retval = reg | (addr & 3);
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} else if (reg & 1) {
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/* CFA1 style */
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retval = (reg & ~7u) | (addr & 7);
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} else {
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uint32_t slot, func;
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/* Grab CFA0 style values */
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slot = ctz32(reg & 0xfffff800);
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if (slot == 32) {
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slot = -1; /* XXX: should this be 0? */
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}
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func = (reg >> 8) & 7;
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/* ... and then convert them to x86 format */
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/* config pointer */
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retval = (reg & (0xff - 7)) | (addr & 7);
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/* slot */
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retval |= slot << 11;
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/* fn */
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retval |= func << 8;
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}
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trace_unin_get_config_reg(reg, addr, retval);
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return retval;
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}
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static void unin_data_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned len)
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{
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UNINState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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trace_unin_data_write(addr, len, val);
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pci_data_write(phb->bus,
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unin_get_config_reg(phb->config_reg, addr),
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val, len);
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}
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static uint64_t unin_data_read(void *opaque, hwaddr addr,
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unsigned len)
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{
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UNINState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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uint32_t val;
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val = pci_data_read(phb->bus,
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unin_get_config_reg(phb->config_reg, addr),
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len);
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trace_unin_data_read(addr, len, val);
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return val;
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}
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static const MemoryRegionOps unin_data_ops = {
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.read = unin_data_read,
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.write = unin_data_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void pci_unin_main_realize(DeviceState *dev, Error **errp)
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{
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UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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h->bus = pci_register_root_bus(dev, NULL,
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pci_unin_set_irq, pci_unin_map_irq,
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s->pic_irqs,
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&s->pci_mmio,
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get_system_io(),
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
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/* DEC 21154 bridge */
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#if 0
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/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
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pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
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#endif
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}
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static void pci_unin_main_init(Object *obj)
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{
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UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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/* Use values found on a real PowerMac */
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/* Uninorth main bus */
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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obj, "unin-pci-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
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"unin-pci-conf-data", 0x1000);
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memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
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0x100000000ULL);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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}
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static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
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{
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UNINState *s = U3_AGP_HOST_BRIDGE(dev);
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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h->bus = pci_register_root_bus(dev, NULL,
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pci_unin_set_irq, pci_unin_map_irq,
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s->pic_irqs,
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&s->pci_mmio,
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get_system_io(),
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
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}
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static void pci_u3_agp_init(Object *obj)
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{
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UNINState *s = U3_AGP_HOST_BRIDGE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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/* Uninorth U3 AGP bus */
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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obj, "unin-pci-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
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"unin-pci-conf-data", 0x1000);
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memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
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0x100000000ULL);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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}
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static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
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{
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UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev);
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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h->bus = pci_register_root_bus(dev, NULL,
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pci_unin_set_irq, pci_unin_map_irq,
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s->pic_irqs,
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&s->pci_mmio,
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get_system_io(),
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
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}
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static void pci_unin_agp_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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/* Uninorth AGP bus */
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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obj, "unin-agp-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
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obj, "unin-agp-conf-data", 0x1000);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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}
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static void pci_unin_internal_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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/* Uninorth internal bus */
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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obj, "unin-pci-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
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obj, "unin-pci-conf-data", 0x1000);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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}
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UNINState *pci_pmac_init(qemu_irq *pic,
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MemoryRegion *address_space_mem)
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{
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DeviceState *dev;
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SysBusDevice *s;
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UNINState *d;
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/* Use values found on a real PowerMac */
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/* Uninorth AGP bus */
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dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
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qdev_prop_set_ptr(dev, "pic-irqs", pic);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(s, 0, 0xf0800000);
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sysbus_mmio_map(s, 1, 0xf0c00000);
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/* Uninorth internal bus */
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#if 0
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/* XXX: not needed for now */
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pci_create_simple(h->bus, PCI_DEVFN(14, 0),
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"uni-north-internal-pci");
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dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(s, 0, 0xf4800000);
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sysbus_mmio_map(s, 1, 0xf4c00000);
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#endif
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/* Uninorth main bus */
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dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
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qdev_prop_set_ptr(dev, "pic-irqs", pic);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
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memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
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0x80000000ULL, 0x10000000ULL);
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memory_region_add_subregion(address_space_mem, 0x80000000ULL,
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&d->pci_hole);
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sysbus_mmio_map(s, 0, 0xf2800000);
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sysbus_mmio_map(s, 1, 0xf2c00000);
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return d;
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}
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UNINState *pci_pmac_u3_init(qemu_irq *pic,
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MemoryRegion *address_space_mem)
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{
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DeviceState *dev;
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SysBusDevice *s;
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UNINState *d;
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/* Uninorth AGP bus */
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dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
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qdev_prop_set_ptr(dev, "pic-irqs", pic);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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d = U3_AGP_HOST_BRIDGE(dev);
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memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
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0x80000000ULL, 0x70000000ULL);
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memory_region_add_subregion(address_space_mem, 0x80000000ULL,
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&d->pci_hole);
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sysbus_mmio_map(s, 0, 0xf0800000);
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sysbus_mmio_map(s, 1, 0xf0c00000);
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return d;
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}
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static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
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{
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/* cache_line_size */
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d->config[0x0C] = 0x08;
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/* latency_timer */
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d->config[0x0D] = 0x10;
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/* capabilities_pointer */
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d->config[0x34] = 0x00;
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/*
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* Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
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* memory space with base 0x80000000, size 0x10000000 for Apple's
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* AppleMacRiscPCI driver
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*/
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d->config[0x48] = 0x0;
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d->config[0x49] = 0x0;
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d->config[0x4a] = 0x0;
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d->config[0x4b] = 0x1;
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}
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static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
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{
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/* cache_line_size */
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d->config[0x0C] = 0x08;
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/* latency_timer */
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d->config[0x0D] = 0x10;
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/* capabilities_pointer
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d->config[0x34] = 0x80; */
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}
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static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
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{
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/* cache line size */
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d->config[0x0C] = 0x08;
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/* latency timer */
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d->config[0x0D] = 0x10;
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}
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static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
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{
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/* cache_line_size */
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d->config[0x0C] = 0x08;
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/* latency_timer */
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d->config[0x0D] = 0x10;
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/* capabilities_pointer */
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d->config[0x34] = 0x00;
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}
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static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = unin_main_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo unin_main_pci_host_info = {
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.name = "uni-north-pci",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = unin_main_pci_host_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = u3_agp_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo u3_agp_pci_host_info = {
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.name = "u3-agp",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = u3_agp_pci_host_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = unin_agp_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo unin_agp_pci_host_info = {
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.name = "uni-north-agp",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = unin_agp_pci_host_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = unin_internal_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
|
|
|
|
static const TypeInfo unin_internal_pci_host_info = {
|
|
.name = "uni-north-internal-pci",
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(PCIDevice),
|
|
.class_init = unin_internal_pci_host_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
{ },
|
|
},
|
|
};
|
|
|
|
static Property pci_unin_main_properties[] = {
|
|
DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void pci_unin_main_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pci_unin_main_realize;
|
|
dc->props = pci_unin_main_properties;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_unin_main_info = {
|
|
.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINState),
|
|
.instance_init = pci_unin_main_init,
|
|
.class_init = pci_unin_main_class_init,
|
|
};
|
|
|
|
static Property pci_u3_agp_properties[] = {
|
|
DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pci_u3_agp_realize;
|
|
dc->props = pci_u3_agp_properties;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_u3_agp_info = {
|
|
.name = TYPE_U3_AGP_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINState),
|
|
.instance_init = pci_u3_agp_init,
|
|
.class_init = pci_u3_agp_class_init,
|
|
};
|
|
|
|
static Property pci_unin_agp_class_properties[] = {
|
|
DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pci_unin_agp_realize;
|
|
dc->props = pci_unin_agp_class_properties;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_unin_agp_info = {
|
|
.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINState),
|
|
.instance_init = pci_unin_agp_init,
|
|
.class_init = pci_unin_agp_class_init,
|
|
};
|
|
|
|
static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_unin_internal_info = {
|
|
.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINState),
|
|
.instance_init = pci_unin_internal_init,
|
|
.class_init = pci_unin_internal_class_init,
|
|
};
|
|
|
|
static void unin_register_types(void)
|
|
{
|
|
type_register_static(&unin_main_pci_host_info);
|
|
type_register_static(&u3_agp_pci_host_info);
|
|
type_register_static(&unin_agp_pci_host_info);
|
|
type_register_static(&unin_internal_pci_host_info);
|
|
|
|
type_register_static(&pci_unin_main_info);
|
|
type_register_static(&pci_u3_agp_info);
|
|
type_register_static(&pci_unin_agp_info);
|
|
type_register_static(&pci_unin_internal_info);
|
|
}
|
|
|
|
type_init(unin_register_types)
|