c165473269
We set default boot order "cad" in every single machine definition except "pseries" and "moxiesim", even though very few boards actually care for boot order, and "cad" makes sense for even fewer. Machines that care: * pc and its variants Accept up to three letters 'a', 'b' (undocumented alias for 'a'), 'c', 'd' and 'n'. Reject all others (fatal with -boot). * nseries (n800, n810) Check whether order starts with 'n'. Silently ignored otherwise. * prep, g3beige, mac99 Extract the first character the machine understands (subset of 'a'..'f'). Silently ignored otherwise. * spapr Accept an arbitrary string (vl.c restricts it to contain only 'a'..'p', no duplicates). * sun4[mdc] Use the first character. Silently ignored otherwise. Strip characters these machines ignore from their default boot order. For all other machines, remove the unused default boot order alltogether. Note that my rename of QEMUMachine member boot_order to default_boot_order and QEMUMachineInitArgs member boot_device to boot_order has a welcome side effect: it makes every use of boot orders visible in this patch, for easy review. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
197 lines
6.8 KiB
C
197 lines
6.8 KiB
C
/*
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* Model of Petalogix linux reference design targeting Xilinx Spartan ml605
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* board.
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*
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* Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (c) 2011 PetaLogix
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* Copyright (c) 2009 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h"
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#include "hw/hw.h"
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#include "net/net.h"
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#include "hw/block/flash.h"
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#include "sysemu/sysemu.h"
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#include "hw/devices.h"
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#include "hw/boards.h"
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#include "hw/xilinx.h"
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#include "sysemu/blockdev.h"
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#include "hw/char/serial.h"
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#include "exec/address-spaces.h"
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#include "hw/ssi.h"
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#include "boot.h"
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#include "pic_cpu.h"
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#include "hw/stream.h"
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#define LMB_BRAM_SIZE (128 * 1024)
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#define FLASH_SIZE (32 * 1024 * 1024)
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#define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
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#define NUM_SPI_FLASHES 4
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#define MEMORY_BASEADDR 0x50000000
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#define FLASH_BASEADDR 0x86000000
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#define INTC_BASEADDR 0x81800000
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#define TIMER_BASEADDR 0x83c00000
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#define UART16550_BASEADDR 0x83e00000
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#define AXIENET_BASEADDR 0x82780000
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#define AXIDMA_BASEADDR 0x84600000
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static void machine_cpu_reset(MicroBlazeCPU *cpu)
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{
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CPUMBState *env = &cpu->env;
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env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
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/* setup pvr to match kernel setting */
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env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK;
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env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI;
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env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
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env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK;
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env->pvr.regs[4] = 0xc56b8000;
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env->pvr.regs[5] = 0xc56be000;
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}
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static void
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petalogix_ml605_init(QEMUMachineInitArgs *args)
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{
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ram_addr_t ram_size = args->ram_size;
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const char *cpu_model = args->cpu_model;
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MemoryRegion *address_space_mem = get_system_memory();
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DeviceState *dev, *dma, *eth0;
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Object *ds, *cs;
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MicroBlazeCPU *cpu;
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SysBusDevice *busdev;
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CPUMBState *env;
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DriveInfo *dinfo;
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int i;
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hwaddr ddr_base = MEMORY_BASEADDR;
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MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
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MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
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qemu_irq irq[32], *cpu_irq;
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/* init CPUs */
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if (cpu_model == NULL) {
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cpu_model = "microblaze";
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}
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cpu = cpu_mb_init(cpu_model);
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env = &cpu->env;
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/* Attach emulated BRAM through the LMB. */
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memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
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LMB_BRAM_SIZE);
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vmstate_register_ram_global(phys_lmb_bram);
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memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
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memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size);
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vmstate_register_ram_global(phys_ram);
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memory_region_add_subregion(address_space_mem, ddr_base, phys_ram);
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dinfo = drive_get(IF_PFLASH, 0, 0);
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/* 5th parameter 2 means bank-width
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* 10th paremeter 0 means little-endian */
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pflash_cfi01_register(FLASH_BASEADDR,
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NULL, "petalogix_ml605.flash", FLASH_SIZE,
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dinfo ? dinfo->bdrv : NULL, (64 * 1024),
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FLASH_SIZE >> 16,
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2, 0x89, 0x18, 0x0000, 0x0, 0);
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cpu_irq = microblaze_pic_init_cpu(env);
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dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 4);
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for (i = 0; i < 32; i++) {
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irq[i] = qdev_get_gpio_in(dev, i);
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}
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serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
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irq[5], 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);
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/* 2 timers at irq 2 @ 100 Mhz. */
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xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 1000000);
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/* axi ethernet and dma initialization. */
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qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet");
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eth0 = qdev_create(NULL, "xlnx.axi-ethernet");
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dma = qdev_create(NULL, "xlnx.axi-dma");
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/* FIXME: attach to the sysbus instead */
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object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0),
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NULL);
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object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma),
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NULL);
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ds = object_property_get_link(OBJECT(dma),
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"axistream-connected-target", NULL);
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cs = object_property_get_link(OBJECT(dma),
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"axistream-control-connected-target", NULL);
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xilinx_axiethernet_init(eth0, &nd_table[0], STREAM_SLAVE(ds),
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STREAM_SLAVE(cs), 0x82780000, irq[3], 0x1000,
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0x1000);
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ds = object_property_get_link(OBJECT(eth0),
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"axistream-connected-target", NULL);
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cs = object_property_get_link(OBJECT(eth0),
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"axistream-control-connected-target", NULL);
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xilinx_axidma_init(dma, STREAM_SLAVE(ds), STREAM_SLAVE(cs), 0x84600000,
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irq[1], irq[0], 100 * 1000000);
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{
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SSIBus *spi;
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dev = qdev_create(NULL, "xlnx.xps-spi");
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qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, 0x40a00000);
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sysbus_connect_irq(busdev, 0, irq[4]);
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spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
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for (i = 0; i < NUM_SPI_FLASHES; i++) {
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qemu_irq cs_line;
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dev = ssi_create_slave(spi, "n25q128");
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cs_line = qdev_get_gpio_in(dev, 0);
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sysbus_connect_irq(busdev, i+1, cs_line);
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}
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}
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microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
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machine_cpu_reset);
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}
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static QEMUMachine petalogix_ml605_machine = {
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.name = "petalogix-ml605",
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.desc = "PetaLogix linux refdesign for xilinx ml605 little endian",
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.init = petalogix_ml605_init,
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.is_default = 0,
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};
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static void petalogix_ml605_machine_init(void)
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{
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qemu_register_machine(&petalogix_ml605_machine);
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}
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machine_init(petalogix_ml605_machine_init);
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