qemu/tests/tcg/aarch64/sve-str.c
Richard Henderson b11293c212 target/arm: Fix SVE STR increment
The previous change missed updating one of the increments and
one of the MemOps.  Add a test case for all vector lengths.

Cc: qemu-stable@nongnu.org
Fixes: e6dd5e782b ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231031143215.29764-1-richard.henderson@linaro.org
[PMM: fixed checkpatch nit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-02 13:36:45 +00:00

50 lines
1008 B
C

#include <stdio.h>
#include <sys/prctl.h>
#define N (256 + 16)
static int __attribute__((noinline)) test(int vl)
{
unsigned char buf[N];
int err = 0;
for (int i = 0; i < N; ++i) {
buf[i] = (unsigned char)i;
}
asm volatile (
"mov z0.b, #255\n\t"
"str z0, %0"
: : "m" (buf) : "z0", "memory");
for (int i = 0; i < vl; ++i) {
if (buf[i] != 0xff) {
fprintf(stderr, "vl %d, index %d, expected 255, got %d\n",
vl, i, buf[i]);
err = 1;
}
}
for (int i = vl; i < N; ++i) {
if (buf[i] != (unsigned char)i) {
fprintf(stderr, "vl %d, index %d, expected %d, got %d\n",
vl, i, (unsigned char)i, buf[i]);
err = 1;
}
}
return err;
}
int main()
{
int err = 0;
for (int i = 16; i <= 256; i += 16) {
if (prctl(PR_SVE_SET_VL, i, 0, 0, 0, 0) == i) {
err |= test(i);
}
}
return err;
}