d2623129a7
The only way object_property_add() can fail is when a property with the same name already exists. Since our property names are all hardcoded, failure is a programming error, and the appropriate way to handle it is passing &error_abort. Same for its variants, except for object_property_add_child(), which additionally fails when the child already has a parent. Parentage is also under program control, so this is a programming error, too. We have a bit over 500 callers. Almost half of them pass &error_abort, slightly fewer ignore errors, one test case handles errors, and the remaining few callers pass them to their own callers. The previous few commits demonstrated once again that ignoring programming errors is a bad idea. Of the few ones that pass on errors, several violate the Error API. The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. ich9_pm_add_properties(), sparc32_ledma_realize(), sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize() are wrong that way. When the one appropriate choice of argument is &error_abort, letting users pick the argument is a bad idea. Drop parameter @errp and assert the preconditions instead. There's one exception to "duplicate property name is a programming error": the way object_property_add() implements the magic (and undocumented) "automatic arrayification". Don't drop @errp there. Instead, rename object_property_add() to object_property_try_add(), and add the obvious wrapper object_property_add(). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200505152926.18877-15-armbru@redhat.com> [Two semantic rebase conflicts resolved]
545 lines
18 KiB
C
545 lines
18 KiB
C
/*
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* ASPEED SoC family
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*
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* Andrew Jeffery <andrew@aj.id.au>
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* Jeremy Kerr <jk@ozlabs.org>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "exec/address-spaces.h"
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#include "hw/misc/unimp.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/char/serial.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#define ASPEED_SOC_IOMEM_SIZE 0x00200000
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static const hwaddr aspeed_soc_ast2400_memmap[] = {
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[ASPEED_IOMEM] = 0x1E600000,
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[ASPEED_FMC] = 0x1E620000,
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[ASPEED_SPI1] = 0x1E630000,
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[ASPEED_EHCI1] = 0x1E6A1000,
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[ASPEED_VIC] = 0x1E6C0000,
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[ASPEED_SDMC] = 0x1E6E0000,
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[ASPEED_SCU] = 0x1E6E2000,
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[ASPEED_XDMA] = 0x1E6E7000,
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[ASPEED_VIDEO] = 0x1E700000,
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[ASPEED_ADC] = 0x1E6E9000,
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[ASPEED_SRAM] = 0x1E720000,
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[ASPEED_SDHCI] = 0x1E740000,
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[ASPEED_GPIO] = 0x1E780000,
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[ASPEED_RTC] = 0x1E781000,
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[ASPEED_TIMER1] = 0x1E782000,
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[ASPEED_WDT] = 0x1E785000,
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[ASPEED_PWM] = 0x1E786000,
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[ASPEED_LPC] = 0x1E789000,
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[ASPEED_IBT] = 0x1E789140,
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[ASPEED_I2C] = 0x1E78A000,
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[ASPEED_ETH1] = 0x1E660000,
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[ASPEED_ETH2] = 0x1E680000,
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[ASPEED_UART1] = 0x1E783000,
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[ASPEED_UART5] = 0x1E784000,
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[ASPEED_VUART] = 0x1E787000,
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[ASPEED_SDRAM] = 0x40000000,
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};
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static const hwaddr aspeed_soc_ast2500_memmap[] = {
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[ASPEED_IOMEM] = 0x1E600000,
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[ASPEED_FMC] = 0x1E620000,
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[ASPEED_SPI1] = 0x1E630000,
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[ASPEED_SPI2] = 0x1E631000,
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[ASPEED_EHCI1] = 0x1E6A1000,
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[ASPEED_EHCI2] = 0x1E6A3000,
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[ASPEED_VIC] = 0x1E6C0000,
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[ASPEED_SDMC] = 0x1E6E0000,
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[ASPEED_SCU] = 0x1E6E2000,
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[ASPEED_XDMA] = 0x1E6E7000,
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[ASPEED_ADC] = 0x1E6E9000,
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[ASPEED_VIDEO] = 0x1E700000,
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[ASPEED_SRAM] = 0x1E720000,
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[ASPEED_SDHCI] = 0x1E740000,
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[ASPEED_GPIO] = 0x1E780000,
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[ASPEED_RTC] = 0x1E781000,
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[ASPEED_TIMER1] = 0x1E782000,
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[ASPEED_WDT] = 0x1E785000,
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[ASPEED_PWM] = 0x1E786000,
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[ASPEED_LPC] = 0x1E789000,
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[ASPEED_IBT] = 0x1E789140,
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[ASPEED_I2C] = 0x1E78A000,
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[ASPEED_ETH1] = 0x1E660000,
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[ASPEED_ETH2] = 0x1E680000,
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[ASPEED_UART1] = 0x1E783000,
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[ASPEED_UART5] = 0x1E784000,
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[ASPEED_VUART] = 0x1E787000,
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[ASPEED_SDRAM] = 0x80000000,
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};
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static const int aspeed_soc_ast2400_irqmap[] = {
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[ASPEED_UART1] = 9,
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[ASPEED_UART2] = 32,
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[ASPEED_UART3] = 33,
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[ASPEED_UART4] = 34,
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[ASPEED_UART5] = 10,
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[ASPEED_VUART] = 8,
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[ASPEED_FMC] = 19,
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[ASPEED_EHCI1] = 5,
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[ASPEED_EHCI2] = 13,
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[ASPEED_SDMC] = 0,
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[ASPEED_SCU] = 21,
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[ASPEED_ADC] = 31,
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[ASPEED_GPIO] = 20,
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[ASPEED_RTC] = 22,
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[ASPEED_TIMER1] = 16,
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[ASPEED_TIMER2] = 17,
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[ASPEED_TIMER3] = 18,
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[ASPEED_TIMER4] = 35,
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[ASPEED_TIMER5] = 36,
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[ASPEED_TIMER6] = 37,
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[ASPEED_TIMER7] = 38,
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[ASPEED_TIMER8] = 39,
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[ASPEED_WDT] = 27,
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[ASPEED_PWM] = 28,
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[ASPEED_LPC] = 8,
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[ASPEED_IBT] = 8, /* LPC */
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[ASPEED_I2C] = 12,
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[ASPEED_ETH1] = 2,
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[ASPEED_ETH2] = 3,
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[ASPEED_XDMA] = 6,
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[ASPEED_SDHCI] = 26,
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};
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#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
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static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
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}
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static void aspeed_soc_init(Object *obj)
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{
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AspeedSoCState *s = ASPEED_SOC(obj);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i;
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char socname[8];
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char typename[64];
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if (sscanf(sc->name, "%7s", socname) != 1) {
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g_assert_not_reached();
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}
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for (i = 0; i < sc->num_cpus; i++) {
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object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
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sizeof(s->cpu[i]), sc->cpu_type,
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&error_abort, NULL);
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}
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snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
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sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
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typename);
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qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
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sc->silicon_rev);
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object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
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"hw-strap1");
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object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
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"hw-strap2");
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object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
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"hw-prot-key");
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sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
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TYPE_ASPEED_VIC);
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sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
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TYPE_ASPEED_RTC);
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snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
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sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
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sizeof(s->timerctrl), typename);
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snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
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sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
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typename);
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snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
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sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
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typename);
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object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
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for (i = 0; i < sc->spis_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
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sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
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sizeof(s->spi[i]), typename);
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}
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for (i = 0; i < sc->ehcis_num; i++) {
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sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
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sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
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}
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snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
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sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
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typename);
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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"ram-size");
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object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
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"max-ram-size");
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for (i = 0; i < sc->wdts_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
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sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
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sizeof(s->wdt[i]), typename);
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}
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for (i = 0; i < sc->macs_num; i++) {
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sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
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sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
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}
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sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
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TYPE_ASPEED_XDMA);
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
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sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
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typename);
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sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
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TYPE_ASPEED_SDHCI);
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object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
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/* Init sd card slot class here so that they're under the correct parent */
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for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
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sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
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sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
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}
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}
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static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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{
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int i;
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AspeedSoCState *s = ASPEED_SOC(dev);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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Error *err = NULL, *local_err = NULL;
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/* IO space */
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create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
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ASPEED_SOC_IOMEM_SIZE);
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/* Video engine stub */
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create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
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0x1000);
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if (s->num_cpus > sc->num_cpus) {
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warn_report("%s: invalid number of CPUs %d, using default %d",
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sc->name, s->num_cpus, sc->num_cpus);
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s->num_cpus = sc->num_cpus;
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}
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/* CPU */
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for (i = 0; i < s->num_cpus; i++) {
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object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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}
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/* SRAM */
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memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
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sc->sram_size, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(get_system_memory(),
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sc->memmap[ASPEED_SRAM], &s->sram);
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/* SCU */
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object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
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/* VIC */
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object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
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/* RTC */
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object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
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aspeed_soc_get_irq(s, ASPEED_RTC));
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/* Timer */
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object_property_set_link(OBJECT(&s->timerctrl),
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OBJECT(&s->scu), "scu", &error_abort);
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object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
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sc->memmap[ASPEED_TIMER1]);
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for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
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qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
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}
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/* UART - attach an 8250 to the IO space as our UART5 */
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if (serial_hd(0)) {
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qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
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serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
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uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
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}
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/* I2C */
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object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
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aspeed_soc_get_irq(s, ASPEED_I2C));
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/* FMC, The number of CS is set at the board level */
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object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
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"sdram-base", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
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s->fmc.ctrl->flash_window_base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
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aspeed_soc_get_irq(s, ASPEED_FMC));
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/* SPI */
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for (i = 0; i < sc->spis_num; i++) {
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object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
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object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
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&local_err);
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error_propagate(&err, local_err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
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sc->memmap[ASPEED_SPI1 + i]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
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s->spi[i].ctrl->flash_window_base);
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}
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/* EHCI */
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for (i = 0; i < sc->ehcis_num; i++) {
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object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
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sc->memmap[ASPEED_EHCI1 + i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
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aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
|
|
}
|
|
|
|
/* SDMC - SDRAM Memory Controller */
|
|
object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
|
|
|
|
/* Watch dog */
|
|
for (i = 0; i < sc->wdts_num; i++) {
|
|
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
|
|
|
|
object_property_set_link(OBJECT(&s->wdt[i]),
|
|
OBJECT(&s->scu), "scu", &error_abort);
|
|
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
|
|
sc->memmap[ASPEED_WDT] + i * awc->offset);
|
|
}
|
|
|
|
/* Net */
|
|
for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
|
|
qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
|
|
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
|
|
&err);
|
|
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
|
|
&local_err);
|
|
error_propagate(&err, local_err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
|
|
sc->memmap[ASPEED_ETH1 + i]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
|
|
}
|
|
|
|
/* XDMA */
|
|
object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
|
|
sc->memmap[ASPEED_XDMA]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_XDMA));
|
|
|
|
/* GPIO */
|
|
object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_GPIO));
|
|
|
|
/* SDHCI */
|
|
object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
|
|
sc->memmap[ASPEED_SDHCI]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_SDHCI));
|
|
}
|
|
static Property aspeed_soc_properties[] = {
|
|
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
|
|
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
|
|
MemoryRegion *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = aspeed_soc_realize;
|
|
/* Reason: Uses serial_hds and nd_table in realize() directly */
|
|
dc->user_creatable = false;
|
|
device_class_set_props(dc, aspeed_soc_properties);
|
|
}
|
|
|
|
static const TypeInfo aspeed_soc_type_info = {
|
|
.name = TYPE_ASPEED_SOC,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(AspeedSoCState),
|
|
.class_size = sizeof(AspeedSoCClass),
|
|
.class_init = aspeed_soc_class_init,
|
|
.abstract = true,
|
|
};
|
|
|
|
static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
|
|
|
|
sc->name = "ast2400-a1";
|
|
sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
|
|
sc->silicon_rev = AST2400_A1_SILICON_REV;
|
|
sc->sram_size = 0x8000;
|
|
sc->spis_num = 1;
|
|
sc->ehcis_num = 1;
|
|
sc->wdts_num = 2;
|
|
sc->macs_num = 2;
|
|
sc->irqmap = aspeed_soc_ast2400_irqmap;
|
|
sc->memmap = aspeed_soc_ast2400_memmap;
|
|
sc->num_cpus = 1;
|
|
}
|
|
|
|
static const TypeInfo aspeed_soc_ast2400_type_info = {
|
|
.name = "ast2400-a1",
|
|
.parent = TYPE_ASPEED_SOC,
|
|
.instance_init = aspeed_soc_init,
|
|
.instance_size = sizeof(AspeedSoCState),
|
|
.class_init = aspeed_soc_ast2400_class_init,
|
|
};
|
|
|
|
static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
|
|
|
|
sc->name = "ast2500-a1";
|
|
sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
|
|
sc->silicon_rev = AST2500_A1_SILICON_REV;
|
|
sc->sram_size = 0x9000;
|
|
sc->spis_num = 2;
|
|
sc->ehcis_num = 2;
|
|
sc->wdts_num = 3;
|
|
sc->macs_num = 2;
|
|
sc->irqmap = aspeed_soc_ast2500_irqmap;
|
|
sc->memmap = aspeed_soc_ast2500_memmap;
|
|
sc->num_cpus = 1;
|
|
}
|
|
|
|
static const TypeInfo aspeed_soc_ast2500_type_info = {
|
|
.name = "ast2500-a1",
|
|
.parent = TYPE_ASPEED_SOC,
|
|
.instance_init = aspeed_soc_init,
|
|
.instance_size = sizeof(AspeedSoCState),
|
|
.class_init = aspeed_soc_ast2500_class_init,
|
|
};
|
|
static void aspeed_soc_register_types(void)
|
|
{
|
|
type_register_static(&aspeed_soc_type_info);
|
|
type_register_static(&aspeed_soc_ast2400_type_info);
|
|
type_register_static(&aspeed_soc_ast2500_type_info);
|
|
};
|
|
|
|
type_init(aspeed_soc_register_types)
|