Leon Alrae bf7910c6b1 target-mips: move PREF, CACHE, LLD and SCD instructions ...

The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

2014-10-13 12:38:24 +01:00

..

cpu-qom.h

target-mips: Use cpu_exec_interrupt qom hook

2014-09-25 18:54:22 +01:00

cpu.c

gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flag

2014-10-06 14:25:43 +01:00

cpu.h

target-mips: implement UserLocal Register

2014-06-18 18:10:47 +02:00

dsp_helper.c

tcg: Invert the inclusion of helper.h

2014-05-28 09:33:54 -07:00

gdbstub.c

cpu: Introduce CPUClass::gdb_{read,write}_register()

2013-07-27 00:04:17 +02:00

helper.c

target-mips: Use cpu_exec_interrupt qom hook

2014-09-25 18:54:22 +01:00

helper.h

tcg: Invert the inclusion of helper.h

2014-05-28 09:33:54 -07:00

kvm_mips.h

target-mips: kvm: Add main KVM support for MIPS

2014-06-18 16:58:52 +02:00

kvm.c

mips/kvm: Disable FPU on reset with KVM

2014-07-09 18:17:04 +02:00

lmi_helper.c

tcg: Invert the inclusion of helper.h

2014-05-28 09:33:54 -07:00

machine.c

target-mips: implement UserLocal Register

2014-06-18 18:10:47 +02:00

Makefile.objs

target-mips: Enable KVM support in build system

2014-06-18 16:59:37 +02:00

mips-defs.h

target-mips: define ISA_MIPS64R6

2014-10-13 12:38:24 +01:00

op_helper.c

target-mips: Ignore unassigned accesses with KVM

2014-08-07 15:09:48 +02:00

TODO

…

translate_init.c

target-mips: Avoid shifting left into sign bit

2014-03-27 19:22:49 +04:00

translate.c

target-mips: move PREF, CACHE, LLD and SCD instructions

2014-10-13 12:38:24 +01:00