6576b74b0b
The official spelling is QEMU. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
97 lines
4.3 KiB
Plaintext
97 lines
4.3 KiB
Plaintext
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Device Specification for Inter-VM shared memory device
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The Inter-VM shared memory device is designed to share a region of memory to
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userspace in multiple virtual guests. The memory region does not belong to any
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guest, but is a POSIX memory object on the host. Optionally, the device may
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support sending interrupts to other guests sharing the same memory region.
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The Inter-VM PCI device
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-----------------------
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*BARs*
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The device supports three BARs. BAR0 is a 1 Kbyte MMIO region to support
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registers. BAR1 is used for MSI-X when it is enabled in the device. BAR2 is
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used to map the shared memory object from the host. The size of BAR2 is
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specified when the guest is started and must be a power of 2 in size.
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*Registers*
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The device currently supports 4 registers of 32-bits each. Registers
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are used for synchronization between guests sharing the same memory object when
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interrupts are supported (this requires using the shared memory server).
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The server assigns each VM an ID number and sends this ID number to the QEMU
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process when the guest starts.
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enum ivshmem_registers {
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IntrMask = 0,
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IntrStatus = 4,
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IVPosition = 8,
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Doorbell = 12
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};
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The first two registers are the interrupt mask and status registers. Mask and
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status are only used with pin-based interrupts. They are unused with MSI
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interrupts.
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Status Register: The status register is set to 1 when an interrupt occurs.
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Mask Register: The mask register is bitwise ANDed with the interrupt status
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and the result will raise an interrupt if it is non-zero. However, since 1 is
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the only value the status will be set to, it is only the first bit of the mask
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that has any effect. Therefore interrupts can be masked by setting the first
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bit to 0 and unmasked by setting the first bit to 1.
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IVPosition Register: The IVPosition register is read-only and reports the
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guest's ID number. The guest IDs are non-negative integers. When using the
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server, since the server is a separate process, the VM ID will only be set when
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the device is ready (shared memory is received from the server and accessible via
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the device). If the device is not ready, the IVPosition will return -1.
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Applications should ensure that they have a valid VM ID before accessing the
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shared memory.
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Doorbell Register: To interrupt another guest, a guest must write to the
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Doorbell register. The doorbell register is 32-bits, logically divided into
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two 16-bit fields. The high 16-bits are the guest ID to interrupt and the low
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16-bits are the interrupt vector to trigger. The semantics of the value
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written to the doorbell depends on whether the device is using MSI or a regular
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pin-based interrupt. In short, MSI uses vectors while regular interrupts set the
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status register.
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Regular Interrupts
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If regular interrupts are used (due to either a guest not supporting MSI or the
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user specifying not to use them on startup) then the value written to the lower
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16-bits of the Doorbell register results is arbitrary and will trigger an
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interrupt in the destination guest.
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Message Signalled Interrupts
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A ivshmem device may support multiple MSI vectors. If so, the lower 16-bits
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written to the Doorbell register must be between 0 and the maximum number of
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vectors the guest supports. The lower 16 bits written to the doorbell is the
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MSI vector that will be raised in the destination guest. The number of MSI
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vectors is configurable but it is set when the VM is started.
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The important thing to remember with MSI is that it is only a signal, no status
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is set (since MSI interrupts are not shared). All information other than the
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interrupt itself should be communicated via the shared memory region. Devices
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supporting multiple MSI vectors can use different vectors to indicate different
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events have occurred. The semantics of interrupt vectors are left to the
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user's discretion.
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Usage in the Guest
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------------------
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The shared memory device is intended to be used with the provided UIO driver.
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Very little configuration is needed. The guest should map BAR0 to access the
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registers (an array of 32-bit ints allows simple writing) and map BAR2 to
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access the shared memory region itself. The size of the shared memory region
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is specified when the guest (or shared memory server) is started. A guest may
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map the whole shared memory region or only part of it.
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