Damien Hedde 38867cb7ec hw/misc/zynq_slcr: add clock generation for uarts ... Add some clocks to zynq_slcr + the main input clock (ps_clk) + the reference clock outputs for each uart (uart0 & 1) This commit also transitional the slcr to multi-phase reset as it is required to initialize the clocks correctly. The clock frequencies are computed using the internal pll & uart configuration registers and the input ps_clk frequency. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200406135251.157596-7-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2020-04-30 15:35:41 +01:00
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macio
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zynq_slcr.c	hw/misc/zynq_slcr: add clock generation for uarts	2020-04-30 15:35:41 +01:00
zynq-xadc.c