qemu/tests/tcg/aarch64/test-2375.c
Richard Henderson 7619129f0d target/arm: Fix FJCVTZS vs flush-to-zero
Input denormals cause the Javascript inexact bit
(output to Z) to be set.

Cc: qemu-stable@nongnu.org
Fixes: 6c1f6f2733 ("target/arm: Implement ARMv8.3-JSConv")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2375
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-4-richard.henderson@linaro.org
[PMM: fixed hardcoded tab in test case]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01 12:48:55 +01:00

22 lines
450 B
C

/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (c) 2024 Linaro Ltd */
/* See https://gitlab.com/qemu-project/qemu/-/issues/2375 */
#include <assert.h>
int main(void)
{
int r, z;
asm("msr fpcr, %2\n\t"
"fjcvtzs %w0, %d3\n\t"
"cset %1, eq"
: "=r"(r), "=r"(z)
: "r"(0x01000000L), /* FZ = 1 */
"w"(0xfcff00L)); /* denormal */
assert(r == 0);
assert(z == 0);
return 0;
}