Pan Nengyuan bb8136df69

riscv/sifive_u: fix a memory leak in soc_realize() ...

Fix a minor memory leak in riscv_sifive_u_soc_realize()

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

2020-01-16 10:02:40 -08:00

..

boot.c

hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()

2019-11-25 12:34:52 -08:00

Kconfig

riscv/virt: Add the PFlash CFI01 device

2019-10-28 07:47:28 -07:00

Makefile.objs

riscv: sifive: Implement a model for SiFive FU540 OTP

2019-09-17 08:42:49 -07:00

riscv_hart.c

riscv: hart: Add a "hartid-base" property to RISC-V hart array

2019-09-17 08:42:47 -07:00

riscv_htif.c

chardev: Use QEMUChrEvent enum in IOEventHandler typedef

2020-01-08 11:15:35 +01:00

sifive_clint.c

…

sifive_e_prci.c

riscv: sifive_e: prci: Update the PRCI register block size

2019-09-17 08:42:46 -07:00

sifive_e.c

hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()

2019-11-25 12:34:52 -08:00

sifive_gpio.c

…

sifive_plic.c

…

sifive_test.c

riscv: hw: Remove the unnecessary include of target/riscv/cpu.h

2019-09-17 08:42:45 -07:00

sifive_u_otp.c

riscv: sifive: Implement a model for SiFive FU540 OTP

2019-09-17 08:42:49 -07:00

sifive_u_prci.c

riscv: sifive: Implement PRCI model for FU540

2019-09-17 08:42:47 -07:00

sifive_u.c

riscv/sifive_u: fix a memory leak in soc_realize()

2020-01-16 10:02:40 -08:00

sifive_uart.c

chardev: Use QEMUChrEvent enum in IOEventHandler typedef

2020-01-08 11:15:35 +01:00

spike.c

hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()

2019-11-25 12:34:52 -08:00

trace-events

…

virt.c

hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()

2019-11-25 12:34:52 -08:00