James Hogan bad63a8008 target/mips: Enable CP0_EBase.WG on MIPS64 CPUs ... Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic CPUs. This allows 64-bit guests to run KVM itself, which uses CP0_EBase.WG to point CP0_EBase at XKPhys. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>		2017-07-21 03:23:44 +01:00
..
cpu-qom.h
cpu.c	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
cpu.h	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
dsp_helper.c
gdbstub.c
helper.c	target/mips: Implement segmentation control	2017-07-20 22:42:26 +01:00
helper.h	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
kvm_mips.h
kvm.c	vcpu_dirty: share the same field in CPUState for all accelerators	2017-07-04 14:30:03 +02:00
lmi_helper.c
machine.c	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
Makefile.objs
mips-defs.h
mips-semi.c
msa_helper.c
op_helper.c	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
TODO
trace-events	target-mips: replace few LOG_DISAS() with trace points	2017-03-20 11:06:32 +00:00
translate_init.c	target/mips: Enable CP0_EBase.WG on MIPS64 CPUs	2017-07-21 03:23:44 +01:00
translate.c	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00