681 lines
20 KiB
C
681 lines
20 KiB
C
/*
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* QEMU PPC PREP hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "hw/timer/m48t59.h"
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#include "hw/i386/pc.h"
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#include "hw/char/serial.h"
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#include "hw/block/fdc.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#include "hw/isa/isa.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/ppc.h"
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#include "hw/boards.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "hw/ide.h"
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#include "hw/loader.h"
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#include "hw/timer/mc146818rtc.h"
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#include "hw/isa/pc87312.h"
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#include "sysemu/block-backend.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/qtest.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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#include "elf.h"
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#include "qemu/cutils.h"
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1
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#define MAX_IDE_BUS 2
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#define BIOS_SIZE (1024 * 1024)
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#define BIOS_FILENAME "ppc_rom.bin"
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#define KERNEL_LOAD_ADDR 0x01000000
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#define INITRD_LOAD_ADDR 0x01800000
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/* Constants for devices init */
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 13, 13 };
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#define NE2000_NB_MAX 6
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static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
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static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
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/* ISA IO ports bridge */
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#define PPC_IO_BASE 0x80000000
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/* PowerPC control and status registers */
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#if 0 // Not used
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static struct {
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/* IDs */
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uint32_t veni_devi;
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uint32_t revi;
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/* Control and status */
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uint32_t gcsr;
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uint32_t xcfr;
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uint32_t ct32;
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uint32_t mcsr;
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/* General purpose registers */
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uint32_t gprg[6];
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/* Exceptions */
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uint32_t feen;
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uint32_t fest;
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uint32_t fema;
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uint32_t fecl;
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uint32_t eeen;
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uint32_t eest;
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uint32_t eecl;
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uint32_t eeint;
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uint32_t eemck0;
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uint32_t eemck1;
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/* Error diagnostic */
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} XCSR;
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static void PPC_XCSR_writeb (void *opaque,
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hwaddr addr, uint32_t value)
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{
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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}
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static void PPC_XCSR_writew (void *opaque,
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hwaddr addr, uint32_t value)
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{
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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}
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static void PPC_XCSR_writel (void *opaque,
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hwaddr addr, uint32_t value)
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{
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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}
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static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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retval);
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return retval;
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}
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static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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retval);
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return retval;
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}
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static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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retval);
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return retval;
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}
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static const MemoryRegionOps PPC_XCSR_ops = {
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.old_mmio = {
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.read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
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.write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#endif
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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typedef struct sysctrl_t {
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qemu_irq reset_irq;
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Nvram *nvram;
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uint8_t state;
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uint8_t syscontrol;
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int contiguous_map;
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qemu_irq contiguous_map_irq;
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int endian;
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} sysctrl_t;
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enum {
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STATE_HARDFILE = 0x01,
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};
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static sysctrl_t *sysctrl;
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static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
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{
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sysctrl_t *sysctrl = opaque;
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trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
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switch (addr) {
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case 0x0092:
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/* Special port 92 */
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/* Check soft reset asked */
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if (val & 0x01) {
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qemu_irq_raise(sysctrl->reset_irq);
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} else {
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qemu_irq_lower(sysctrl->reset_irq);
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}
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/* Check LE mode */
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if (val & 0x02) {
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sysctrl->endian = 1;
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} else {
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sysctrl->endian = 0;
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}
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break;
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case 0x0800:
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/* Motorola CPU configuration register : read-only */
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break;
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case 0x0802:
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/* Motorola base module feature register : read-only */
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break;
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case 0x0803:
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/* Motorola base module status register : read-only */
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break;
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case 0x0808:
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/* Hardfile light register */
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if (val & 1)
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sysctrl->state |= STATE_HARDFILE;
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else
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sysctrl->state &= ~STATE_HARDFILE;
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break;
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case 0x0810:
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/* Password protect 1 register */
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if (sysctrl->nvram != NULL) {
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->toggle_lock)(sysctrl->nvram, 1);
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}
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break;
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case 0x0812:
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/* Password protect 2 register */
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if (sysctrl->nvram != NULL) {
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->toggle_lock)(sysctrl->nvram, 2);
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}
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break;
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case 0x0814:
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/* L2 invalidate register */
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// tlb_flush(first_cpu, 1);
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break;
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case 0x081C:
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/* system control register */
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sysctrl->syscontrol = val & 0x0F;
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break;
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case 0x0850:
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/* I/O map type register */
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sysctrl->contiguous_map = val & 0x01;
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qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
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break;
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default:
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printf("ERROR: unaffected IO port write: %04" PRIx32
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" => %02" PRIx32"\n", addr, val);
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break;
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}
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}
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static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t retval = 0xFF;
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switch (addr) {
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case 0x0092:
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/* Special port 92 */
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retval = sysctrl->endian << 1;
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break;
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case 0x0800:
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/* Motorola CPU configuration register */
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retval = 0xEF; /* MPC750 */
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break;
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case 0x0802:
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/* Motorola Base module feature register */
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retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
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break;
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case 0x0803:
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/* Motorola base module status register */
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retval = 0xE0; /* Standard MPC750 */
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break;
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case 0x080C:
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/* Equipment present register:
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* no L2 cache
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* no upgrade processor
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* no cards in PCI slots
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* SCSI fuse is bad
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*/
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retval = 0x3C;
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break;
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case 0x0810:
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/* Motorola base module extended feature register */
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retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
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break;
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case 0x0814:
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/* L2 invalidate: don't care */
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break;
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case 0x0818:
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/* Keylock */
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retval = 0x00;
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break;
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case 0x081C:
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/* system control register
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* 7 - 6 / 1 - 0: L2 cache enable
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*/
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retval = sysctrl->syscontrol;
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break;
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case 0x0823:
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/* */
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retval = 0x03; /* no L2 cache */
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break;
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case 0x0850:
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/* I/O map type register */
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retval = sysctrl->contiguous_map;
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break;
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default:
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printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
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break;
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}
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trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
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return retval;
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}
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#define NVRAM_SIZE 0x2000
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static void ppc_prep_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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}
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static const MemoryRegionPortio prep_portio_list[] = {
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/* System control ports */
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{ 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
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{ 0x0800, 0x52, 1,
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.read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
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/* Special port to get debug messages from Open-Firmware */
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{ 0x0F00, 4, 1, .write = PPC_debug_write, },
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PORTIO_END_OF_LIST(),
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};
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static PortioList prep_port_list;
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/*****************************************************************************/
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/* NVRAM helpers */
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static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
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{
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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return (k->read)(nvram, addr);
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}
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static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
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{
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->write)(nvram, addr, val);
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}
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static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
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{
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nvram_write(nvram, addr, value);
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}
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static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
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{
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return nvram_read(nvram, addr);
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}
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static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
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{
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nvram_write(nvram, addr, value >> 8);
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nvram_write(nvram, addr + 1, value & 0xFF);
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}
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static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
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{
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uint16_t tmp;
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tmp = nvram_read(nvram, addr) << 8;
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tmp |= nvram_read(nvram, addr + 1);
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return tmp;
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}
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static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
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{
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nvram_write(nvram, addr, value >> 24);
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nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
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nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
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nvram_write(nvram, addr + 3, value & 0xFF);
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}
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static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
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uint32_t max)
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{
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int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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nvram_write(nvram, addr + i, str[i]);
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}
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nvram_write(nvram, addr + i, str[i]);
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nvram_write(nvram, addr + max - 1, '\0');
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}
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static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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{
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uint16_t tmp;
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uint16_t pd, pd1, pd2;
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tmp = prev >> 8;
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pd = prev ^ value;
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pd1 = pd & 0x000F;
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pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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tmp ^= (pd1 << 3) | (pd1 << 8);
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tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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return tmp;
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}
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static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
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{
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uint32_t i;
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uint16_t crc = 0xFFFF;
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int odd;
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odd = count & 1;
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count &= ~1;
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for (i = 0; i != count; i++) {
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crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
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}
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if (odd) {
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crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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}
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return crc;
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}
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#define CMDLINE_ADDR 0x017ff000
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static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
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const char *arch,
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uint32_t RAM_size, int boot_device,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth)
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{
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uint16_t crc;
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/* Set parameters for Open Hack'Ware BIOS */
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NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
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NVRAM_set_word(nvram, 0x14, NVRAM_size);
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NVRAM_set_string(nvram, 0x20, arch, 16);
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NVRAM_set_lword(nvram, 0x30, RAM_size);
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NVRAM_set_byte(nvram, 0x34, boot_device);
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NVRAM_set_lword(nvram, 0x38, kernel_image);
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NVRAM_set_lword(nvram, 0x3C, kernel_size);
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if (cmdline) {
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/* XXX: put the cmdline in NVRAM too ? */
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pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
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cmdline);
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NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
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NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
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} else {
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NVRAM_set_lword(nvram, 0x40, 0);
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NVRAM_set_lword(nvram, 0x44, 0);
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}
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NVRAM_set_lword(nvram, 0x48, initrd_image);
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NVRAM_set_lword(nvram, 0x4C, initrd_size);
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NVRAM_set_lword(nvram, 0x50, NVRAM_image);
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NVRAM_set_word(nvram, 0x54, width);
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NVRAM_set_word(nvram, 0x56, height);
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NVRAM_set_word(nvram, 0x58, depth);
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crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
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NVRAM_set_word(nvram, 0xFC, crc);
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return 0;
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}
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/* PowerPC PREP hardware initialisation */
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static void ppc_prep_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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const char *boot_device = machine->boot_order;
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MemoryRegion *sysmem = get_system_memory();
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PowerPCCPU *cpu = NULL;
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CPUPPCState *env = NULL;
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Nvram *m48t59;
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#if 0
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MemoryRegion *xcsr = g_new(MemoryRegion, 1);
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#endif
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int linux_boot, i, nb_nics1;
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MemoryRegion *ram = g_new(MemoryRegion, 1);
|
|
uint32_t kernel_base, initrd_base;
|
|
long kernel_size, initrd_size;
|
|
DeviceState *dev;
|
|
PCIHostState *pcihost;
|
|
PCIBus *pci_bus;
|
|
PCIDevice *pci;
|
|
ISABus *isa_bus;
|
|
ISADevice *isa;
|
|
int ppc_boot_device;
|
|
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
|
|
|
|
sysctrl = g_malloc0(sizeof(sysctrl_t));
|
|
|
|
linux_boot = (kernel_filename != NULL);
|
|
|
|
/* init CPUs */
|
|
if (machine->cpu_model == NULL)
|
|
machine->cpu_model = "602";
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
cpu = cpu_ppc_init(machine->cpu_model);
|
|
if (cpu == NULL) {
|
|
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
|
exit(1);
|
|
}
|
|
env = &cpu->env;
|
|
|
|
if (env->flags & POWERPC_FLAG_RTC_CLK) {
|
|
/* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
|
|
cpu_ppc_tb_init(env, 7812500UL);
|
|
} else {
|
|
/* Set time-base frequency to 100 Mhz */
|
|
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
|
|
}
|
|
qemu_register_reset(ppc_prep_reset, cpu);
|
|
}
|
|
|
|
/* allocate RAM */
|
|
memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
|
|
memory_region_add_subregion(sysmem, 0, ram);
|
|
|
|
if (linux_boot) {
|
|
kernel_base = KERNEL_LOAD_ADDR;
|
|
/* now we can load the kernel */
|
|
kernel_size = load_image_targphys(kernel_filename, kernel_base,
|
|
ram_size - kernel_base);
|
|
if (kernel_size < 0) {
|
|
error_report("could not load kernel '%s'", kernel_filename);
|
|
exit(1);
|
|
}
|
|
/* load initrd */
|
|
if (initrd_filename) {
|
|
initrd_base = INITRD_LOAD_ADDR;
|
|
initrd_size = load_image_targphys(initrd_filename, initrd_base,
|
|
ram_size - initrd_base);
|
|
if (initrd_size < 0) {
|
|
error_report("could not load initial ram disk '%s'",
|
|
initrd_filename);
|
|
exit(1);
|
|
}
|
|
} else {
|
|
initrd_base = 0;
|
|
initrd_size = 0;
|
|
}
|
|
ppc_boot_device = 'm';
|
|
} else {
|
|
kernel_base = 0;
|
|
kernel_size = 0;
|
|
initrd_base = 0;
|
|
initrd_size = 0;
|
|
ppc_boot_device = '\0';
|
|
/* For now, OHW cannot boot from the network. */
|
|
for (i = 0; boot_device[i] != '\0'; i++) {
|
|
if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
|
|
ppc_boot_device = boot_device[i];
|
|
break;
|
|
}
|
|
}
|
|
if (ppc_boot_device == '\0') {
|
|
fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
|
error_report("Only 6xx bus is supported on PREP machine");
|
|
exit(1);
|
|
}
|
|
|
|
dev = qdev_create(NULL, "raven-pcihost");
|
|
if (bios_name == NULL) {
|
|
bios_name = BIOS_FILENAME;
|
|
}
|
|
qdev_prop_set_string(dev, "bios-name", bios_name);
|
|
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
|
|
pcihost = PCI_HOST_BRIDGE(dev);
|
|
object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
|
|
qdev_init_nofail(dev);
|
|
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
|
if (pci_bus == NULL) {
|
|
fprintf(stderr, "Couldn't create PCI host controller.\n");
|
|
exit(1);
|
|
}
|
|
sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
|
|
|
|
/* PCI -> ISA bridge */
|
|
pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
|
|
cpu = POWERPC_CPU(first_cpu);
|
|
qdev_connect_gpio_out(&pci->qdev, 0,
|
|
cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
|
|
sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
|
|
sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
|
|
sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
|
|
sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
|
|
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
|
|
|
|
/* Super I/O (parallel + serial ports) */
|
|
isa = isa_create(isa_bus, TYPE_PC87312);
|
|
dev = DEVICE(isa);
|
|
qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
|
|
qdev_init_nofail(dev);
|
|
|
|
/* init basic PC hardware */
|
|
pci_vga_init(pci_bus);
|
|
|
|
nb_nics1 = nb_nics;
|
|
if (nb_nics1 > NE2000_NB_MAX)
|
|
nb_nics1 = NE2000_NB_MAX;
|
|
for(i = 0; i < nb_nics1; i++) {
|
|
if (nd_table[i].model == NULL) {
|
|
nd_table[i].model = g_strdup("ne2k_isa");
|
|
}
|
|
if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
|
|
isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
|
|
&nd_table[i]);
|
|
} else {
|
|
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
|
|
}
|
|
}
|
|
|
|
ide_drive_get(hd, ARRAY_SIZE(hd));
|
|
for(i = 0; i < MAX_IDE_BUS; i++) {
|
|
isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
|
|
hd[2 * i],
|
|
hd[2 * i + 1]);
|
|
}
|
|
isa_create_simple(isa_bus, "i8042");
|
|
|
|
cpu = POWERPC_CPU(first_cpu);
|
|
sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
|
|
|
|
portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
|
|
portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
|
|
|
|
/* PowerPC control and status register group */
|
|
#if 0
|
|
memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
|
|
memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
|
|
#endif
|
|
|
|
if (usb_enabled()) {
|
|
pci_create_simple(pci_bus, -1, "pci-ohci");
|
|
}
|
|
|
|
m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
|
|
if (m48t59 == NULL)
|
|
return;
|
|
sysctrl->nvram = m48t59;
|
|
|
|
/* Initialise NVRAM */
|
|
PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
|
|
ppc_boot_device,
|
|
kernel_base, kernel_size,
|
|
kernel_cmdline,
|
|
initrd_base, initrd_size,
|
|
/* XXX: need an option to load a NVRAM image */
|
|
0,
|
|
graphic_width, graphic_height, graphic_depth);
|
|
}
|
|
|
|
static void prep_machine_init(MachineClass *mc)
|
|
{
|
|
mc->desc = "PowerPC PREP platform";
|
|
mc->init = ppc_prep_init;
|
|
mc->max_cpus = MAX_CPUS;
|
|
mc->default_boot_order = "cad";
|
|
}
|
|
|
|
DEFINE_MACHINE("prep", prep_machine_init)
|