qemu/accel
Richard Henderson 6d3ef04893 tcg: Use memset for large vector byte replication
In f47db80cc0, we handled odd-sized tail clearing for
the case of hosts that have vector operations, but did
not handle the case of hosts that do not have vector ops.

This was ok until e2e7168a21, which changed the encoding
of simd_desc such that the odd sizes are impossible.

Add memset as a tcg helper, and use that for all out-of-line
byte stores to vectors.  This includes, but is not limited to,
the tail clearing operation in question.

Cc: qemu-stable@nongnu.org
Buglink: https://bugs.launchpad.net/bugs/1907817
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-04 06:32:58 -10:00
..
kvm kvm: Take into account the unaligned section size when preparing bitmap 2020-12-15 12:52:05 -05:00
qtest accel: move qtest CpusAccel functions to a common location 2020-10-24 07:23:19 +02:00
stubs accel/stubs: drop unused cpu.h include 2020-11-16 11:07:56 +00:00
tcg tcg: Use memset for large vector byte replication 2021-01-04 06:32:58 -10:00
xen accel: Add xen CpusAccel using dummy-cpus 2020-10-24 07:23:19 +02:00
accel.c accel: Introduce the current_accel() wrapper 2020-01-24 20:59:11 +01:00
dummy-cpus.c accel: move qtest CpusAccel functions to a common location 2020-10-24 07:23:19 +02:00
Kconfig accel/Kconfig: Add the TCG selector 2020-07-10 18:02:21 -04:00
meson.build accel: Add xen CpusAccel using dummy-cpus 2020-10-24 07:23:19 +02:00