ba9a74dae0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1937 c046a42c-6fe2-441c-8c8c-71466251a162
750 lines
18 KiB
C
750 lines
18 KiB
C
/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h"
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#define MIPS_DEBUG_DISAS
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#define GETPC() (__builtin_return_address(0))
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/*****************************************************************************/
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/* Exceptions processing helpers */
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void cpu_loop_exit(void)
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{
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longjmp(env->jmp_env, 1);
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}
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void do_raise_exception_err (uint32_t exception, int error_code)
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{
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#if 1
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if (logfile && exception < 0x100)
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fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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#endif
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env->exception_index = exception;
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env->error_code = error_code;
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T0 = 0;
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cpu_loop_exit();
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}
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void do_raise_exception (uint32_t exception)
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{
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do_raise_exception_err(exception, 0);
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}
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void do_restore_state (void *pc_ptr)
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{
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TranslationBlock *tb;
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unsigned long pc = (unsigned long) pc_ptr;
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tb = tb_find_pc (pc);
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cpu_restore_state (tb, env, pc, NULL);
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}
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void do_raise_exception_direct (uint32_t exception)
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{
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do_restore_state (GETPC ());
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do_raise_exception_err (exception, 0);
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}
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#define MEMSUFFIX _raw
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#include "op_helper_mem.c"
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_helper_mem.c"
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_helper_mem.c"
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#undef MEMSUFFIX
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#endif
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/* 64 bits arithmetic for 32 bits hosts */
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#if (HOST_LONG_BITS == 32)
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static inline uint64_t get_HILO (void)
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{
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return ((uint64_t)env->HI << 32) | (uint64_t)env->LO;
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}
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static inline void set_HILO (uint64_t HILO)
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{
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env->LO = HILO & 0xFFFFFFFF;
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env->HI = HILO >> 32;
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}
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void do_mult (void)
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{
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set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
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}
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void do_multu (void)
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{
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set_HILO((uint64_t)T0 * (uint64_t)T1);
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}
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void do_madd (void)
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{
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int64_t tmp;
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tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
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set_HILO((int64_t)get_HILO() + tmp);
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}
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void do_maddu (void)
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{
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uint64_t tmp;
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tmp = ((uint64_t)T0 * (uint64_t)T1);
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set_HILO(get_HILO() + tmp);
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}
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void do_msub (void)
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{
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int64_t tmp;
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tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
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set_HILO((int64_t)get_HILO() - tmp);
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}
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void do_msubu (void)
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{
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uint64_t tmp;
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tmp = ((uint64_t)T0 * (uint64_t)T1);
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set_HILO(get_HILO() - tmp);
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}
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#endif
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#if defined(CONFIG_USER_ONLY)
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void do_mfc0 (int reg, int sel)
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{
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cpu_abort(env, "mfc0 reg=%d sel=%d\n", reg, sel);
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}
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void do_mtc0 (int reg, int sel)
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{
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cpu_abort(env, "mtc0 reg=%d sel=%d\n", reg, sel);
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}
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void do_tlbwi (void)
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{
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cpu_abort(env, "tlbwi\n");
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}
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void do_tlbwr (void)
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{
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cpu_abort(env, "tlbwr\n");
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}
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void do_tlbp (void)
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{
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cpu_abort(env, "tlbp\n");
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}
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void do_tlbr (void)
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{
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cpu_abort(env, "tlbr\n");
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}
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#else
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/* CP0 helpers */
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void do_mfc0 (int reg, int sel)
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{
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const unsigned char *rn;
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if (sel != 0 && reg != 16 && reg != 28) {
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rn = "invalid";
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goto print;
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}
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switch (reg) {
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case 0:
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T0 = env->CP0_index;
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rn = "Index";
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break;
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case 1:
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T0 = cpu_mips_get_random(env);
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rn = "Random";
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break;
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case 2:
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T0 = env->CP0_EntryLo0;
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rn = "EntryLo0";
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break;
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case 3:
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T0 = env->CP0_EntryLo1;
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rn = "EntryLo1";
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break;
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case 4:
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T0 = env->CP0_Context;
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rn = "Context";
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break;
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case 5:
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T0 = env->CP0_PageMask;
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rn = "PageMask";
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break;
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case 6:
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T0 = env->CP0_Wired;
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rn = "Wired";
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break;
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case 8:
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T0 = env->CP0_BadVAddr;
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rn = "BadVaddr";
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break;
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case 9:
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T0 = cpu_mips_get_count(env);
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rn = "Count";
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break;
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case 10:
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T0 = env->CP0_EntryHi;
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rn = "EntryHi";
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break;
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case 11:
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T0 = env->CP0_Compare;
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rn = "Compare";
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break;
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case 12:
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T0 = env->CP0_Status;
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if (env->hflags & MIPS_HFLAG_UM)
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T0 |= (1 << CP0St_UM);
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if (env->hflags & MIPS_HFLAG_ERL)
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T0 |= (1 << CP0St_ERL);
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if (env->hflags & MIPS_HFLAG_EXL)
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T0 |= (1 << CP0St_EXL);
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rn = "Status";
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break;
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case 13:
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T0 = env->CP0_Cause;
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rn = "Cause";
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break;
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case 14:
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T0 = env->CP0_EPC;
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rn = "EPC";
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break;
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case 15:
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T0 = env->CP0_PRid;
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rn = "PRid";
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break;
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case 16:
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switch (sel) {
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case 0:
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T0 = env->CP0_Config0;
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rn = "Config";
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break;
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case 1:
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T0 = env->CP0_Config1;
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rn = "Config1";
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break;
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default:
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rn = "Unknown config register";
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break;
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}
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break;
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case 17:
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T0 = env->CP0_LLAddr >> 4;
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rn = "LLAddr";
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break;
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case 18:
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T0 = env->CP0_WatchLo;
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rn = "WatchLo";
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break;
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case 19:
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T0 = env->CP0_WatchHi;
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rn = "WatchHi";
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break;
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case 23:
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T0 = env->CP0_Debug;
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if (env->hflags & MIPS_HFLAG_DM)
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T0 |= 1 << CP0DB_DM;
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rn = "Debug";
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break;
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case 24:
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T0 = env->CP0_DEPC;
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rn = "DEPC";
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break;
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case 28:
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switch (sel) {
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case 0:
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T0 = env->CP0_TagLo;
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rn = "TagLo";
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break;
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case 1:
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T0 = env->CP0_DataLo;
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rn = "DataLo";
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break;
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default:
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rn = "unknown sel";
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break;
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}
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break;
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case 30:
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T0 = env->CP0_ErrorEPC;
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rn = "ErrorEPC";
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break;
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case 31:
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T0 = env->CP0_DESAVE;
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rn = "DESAVE";
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break;
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default:
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rn = "unknown";
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break;
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}
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print:
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#if defined MIPS_DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "%08x mfc0 %s => %08x (%d %d)\n",
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env->PC, rn, T0, reg, sel);
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}
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#endif
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return;
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}
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void do_mtc0 (int reg, int sel)
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{
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const unsigned char *rn;
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uint32_t val, old, mask;
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if (sel != 0 && reg != 16 && reg != 28) {
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val = -1;
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old = -1;
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rn = "invalid";
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goto print;
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}
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switch (reg) {
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case 0:
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val = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F);
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old = env->CP0_index;
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env->CP0_index = val;
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rn = "Index";
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break;
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case 2:
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val = T0 & 0x3FFFFFFF;
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old = env->CP0_EntryLo0;
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env->CP0_EntryLo0 = val;
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rn = "EntryLo0";
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break;
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case 3:
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val = T0 & 0x3FFFFFFF;
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old = env->CP0_EntryLo1;
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env->CP0_EntryLo1 = val;
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rn = "EntryLo1";
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break;
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case 4:
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val = (env->CP0_Context & 0xFF800000) | (T0 & 0x007FFFF0);
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old = env->CP0_Context;
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env->CP0_Context = val;
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rn = "Context";
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break;
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case 5:
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val = T0 & 0x01FFE000;
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old = env->CP0_PageMask;
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env->CP0_PageMask = val;
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rn = "PageMask";
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break;
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case 6:
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val = T0 & 0x0000000F;
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old = env->CP0_Wired;
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env->CP0_Wired = val;
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rn = "Wired";
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break;
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case 9:
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val = T0;
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old = cpu_mips_get_count(env);
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cpu_mips_store_count(env, val);
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rn = "Count";
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break;
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case 10:
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val = T0 & 0xFFFFE0FF;
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old = env->CP0_EntryHi;
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env->CP0_EntryHi = val;
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/* If the ASID changes, flush qemu's TLB. */
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if ((old & 0xFF) != (val & 0xFF))
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tlb_flush (env, 1);
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rn = "EntryHi";
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break;
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case 11:
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val = T0;
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old = env->CP0_Compare;
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cpu_mips_store_compare(env, val);
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rn = "Compare";
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break;
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case 12:
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val = T0 & 0xFA78FF01;
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if (T0 & (1 << CP0St_UM))
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env->hflags |= MIPS_HFLAG_UM;
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else
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env->hflags &= ~MIPS_HFLAG_UM;
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if (T0 & (1 << CP0St_ERL))
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env->hflags |= MIPS_HFLAG_ERL;
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else
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env->hflags &= ~MIPS_HFLAG_ERL;
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if (T0 & (1 << CP0St_EXL))
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env->hflags |= MIPS_HFLAG_EXL;
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else
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env->hflags &= ~MIPS_HFLAG_EXL;
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old = env->CP0_Status;
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env->CP0_Status = val;
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/* If we unmasked an asserted IRQ, raise it */
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mask = 0x0000FF00;
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
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old, val, env->CP0_Cause, old & mask, val & mask,
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env->CP0_Cause & mask);
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}
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if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) &&
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!(env->hflags & MIPS_HFLAG_EXL) &&
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!(env->hflags & MIPS_HFLAG_ERL) &&
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!(env->hflags & MIPS_HFLAG_DM) &&
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(env->CP0_Status & env->CP0_Cause & mask)) {
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if (logfile)
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fprintf(logfile, "Raise pending IRQs\n");
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env->interrupt_request |= CPU_INTERRUPT_HARD;
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} else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) {
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env->interrupt_request &= ~CPU_INTERRUPT_HARD;
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}
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rn = "Status";
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break;
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case 13:
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val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300);
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old = env->CP0_Cause;
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env->CP0_Cause = val;
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#if 0
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{
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int i;
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/* Check if we ever asserted a software IRQ */
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for (i = 0; i < 2; i++) {
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mask = 0x100 << i;
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if ((val & mask) & !(old & mask))
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mips_set_irq(i);
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}
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}
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#endif
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rn = "Cause";
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break;
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case 14:
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val = T0;
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old = env->CP0_EPC;
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env->CP0_EPC = val;
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rn = "EPC";
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break;
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case 16:
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switch (sel) {
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case 0:
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#if defined(MIPS_USES_R4K_TLB)
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val = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001);
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#else
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val = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001);
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#endif
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old = env->CP0_Config0;
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env->CP0_Config0 = val;
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rn = "Config0";
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break;
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default:
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val = -1;
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old = -1;
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rn = "bad config selector";
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break;
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}
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break;
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case 18:
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val = T0;
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old = env->CP0_WatchLo;
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env->CP0_WatchLo = val;
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rn = "WatchLo";
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break;
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case 19:
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val = T0 & 0x40FF0FF8;
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old = env->CP0_WatchHi;
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env->CP0_WatchHi = val;
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rn = "WatchHi";
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break;
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case 23:
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val = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
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if (T0 & (1 << CP0DB_DM))
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env->hflags |= MIPS_HFLAG_DM;
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else
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env->hflags &= ~MIPS_HFLAG_DM;
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old = env->CP0_Debug;
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env->CP0_Debug = val;
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rn = "Debug";
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break;
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case 24:
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val = T0;
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old = env->CP0_DEPC;
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env->CP0_DEPC = val;
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rn = "DEPC";
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break;
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case 28:
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switch (sel) {
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case 0:
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val = T0 & 0xFFFFFCF6;
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old = env->CP0_TagLo;
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env->CP0_TagLo = val;
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rn = "TagLo";
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break;
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default:
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val = -1;
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old = -1;
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rn = "invalid sel";
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break;
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}
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break;
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case 30:
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val = T0;
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old = env->CP0_ErrorEPC;
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env->CP0_ErrorEPC = val;
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rn = "EPC";
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break;
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case 31:
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val = T0;
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old = env->CP0_DESAVE;
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env->CP0_DESAVE = val;
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rn = "DESAVE";
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break;
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default:
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val = -1;
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old = -1;
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rn = "unknown";
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break;
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}
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print:
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#if defined MIPS_DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "%08x mtc0 %s %08x => %08x (%d %d %08x)\n",
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env->PC, rn, T0, val, reg, sel, old);
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}
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#endif
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return;
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}
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/* TLB management */
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#if defined(MIPS_USES_R4K_TLB)
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static void invalidate_tlb (int idx)
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{
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tlb_t *tlb;
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target_ulong addr;
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tlb = &env->tlb[idx];
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if (tlb->V0) {
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tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN);
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addr = tlb->VPN;
|
|
while (addr < tlb->end) {
|
|
tlb_flush_page (env, addr);
|
|
addr += TARGET_PAGE_SIZE;
|
|
}
|
|
}
|
|
if (tlb->V1) {
|
|
tb_invalidate_page_range(tlb->PFN[1], tlb->end2 - tlb->end);
|
|
addr = tlb->end;
|
|
while (addr < tlb->end2) {
|
|
tlb_flush_page (env, addr);
|
|
addr += TARGET_PAGE_SIZE;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void fill_tlb (int idx)
|
|
{
|
|
tlb_t *tlb;
|
|
int size;
|
|
|
|
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
|
tlb = &env->tlb[idx];
|
|
tlb->VPN = env->CP0_EntryHi & 0xFFFFE000;
|
|
tlb->ASID = env->CP0_EntryHi & 0xFF;
|
|
size = env->CP0_PageMask >> 13;
|
|
size = 4 * (size + 1);
|
|
tlb->end = tlb->VPN + (1 << (8 + size));
|
|
tlb->end2 = tlb->end + (1 << (8 + size));
|
|
tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
|
tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
|
|
tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
|
|
tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
|
|
tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
|
|
tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
|
|
tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
|
|
tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
|
|
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
|
|
}
|
|
|
|
void do_tlbwi (void)
|
|
{
|
|
/* Wildly undefined effects for CP0_index containing a too high value and
|
|
MIPS_TLB_NB not being a power of two. But so does real silicon. */
|
|
invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
|
|
fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
|
|
}
|
|
|
|
void do_tlbwr (void)
|
|
{
|
|
int r = cpu_mips_get_random(env);
|
|
|
|
invalidate_tlb(r);
|
|
fill_tlb(r);
|
|
}
|
|
|
|
void do_tlbp (void)
|
|
{
|
|
tlb_t *tlb;
|
|
target_ulong tag;
|
|
uint8_t ASID;
|
|
int i;
|
|
|
|
tag = env->CP0_EntryHi & 0xFFFFE000;
|
|
ASID = env->CP0_EntryHi & 0xFF;
|
|
for (i = 0; i < MIPS_TLB_NB; i++) {
|
|
tlb = &env->tlb[i];
|
|
/* Check ASID, virtual page number & size */
|
|
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
|
|
/* TLB match */
|
|
env->CP0_index = i;
|
|
break;
|
|
}
|
|
}
|
|
if (i == MIPS_TLB_NB) {
|
|
env->CP0_index |= 0x80000000;
|
|
}
|
|
}
|
|
|
|
void do_tlbr (void)
|
|
{
|
|
tlb_t *tlb;
|
|
uint8_t ASID;
|
|
int size;
|
|
|
|
ASID = env->CP0_EntryHi & 0xFF;
|
|
tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
|
|
|
|
/* If this will change the current ASID, flush qemu's TLB. */
|
|
if (ASID != tlb->ASID && tlb->G != 1)
|
|
tlb_flush (env, 1);
|
|
|
|
env->CP0_EntryHi = tlb->VPN | tlb->ASID;
|
|
size = (tlb->end - tlb->VPN) >> 12;
|
|
env->CP0_PageMask = (size - 1) << 13;
|
|
env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2)
|
|
| (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
|
|
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2)
|
|
| (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
|
|
}
|
|
#endif
|
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
void op_dump_ldst (const unsigned char *func)
|
|
{
|
|
if (loglevel)
|
|
fprintf(logfile, "%s => %08x %08x\n", __func__, T0, T1);
|
|
}
|
|
|
|
void dump_sc (void)
|
|
{
|
|
if (loglevel) {
|
|
fprintf(logfile, "%s %08x at %08x (%08x)\n", __func__,
|
|
T1, T0, env->CP0_LLAddr);
|
|
}
|
|
}
|
|
|
|
void debug_eret (void)
|
|
{
|
|
if (loglevel) {
|
|
fprintf(logfile, "ERET: pc %08x EPC %08x ErrorEPC %08x (%d)\n",
|
|
env->PC, env->CP0_EPC, env->CP0_ErrorEPC,
|
|
env->hflags & MIPS_HFLAG_ERL ? 1 : 0);
|
|
}
|
|
}
|
|
|
|
void do_pmon (int function)
|
|
{
|
|
function /= 2;
|
|
switch (function) {
|
|
case 2: /* TODO: char inbyte(int waitflag); */
|
|
if (env->gpr[4] == 0)
|
|
env->gpr[2] = -1;
|
|
/* Fall through */
|
|
case 11: /* TODO: char inbyte (void); */
|
|
env->gpr[2] = -1;
|
|
break;
|
|
case 3:
|
|
case 12:
|
|
printf("%c", env->gpr[4] & 0xFF);
|
|
break;
|
|
case 17:
|
|
break;
|
|
case 158:
|
|
{
|
|
unsigned char *fmt = (void *)env->gpr[4];
|
|
printf("%s", fmt);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
|
|
|
|
#define MMUSUFFIX _mmu
|
|
#define ALIGNED_ONLY
|
|
|
|
#define SHIFT 0
|
|
#include "softmmu_template.h"
|
|
|
|
#define SHIFT 1
|
|
#include "softmmu_template.h"
|
|
|
|
#define SHIFT 2
|
|
#include "softmmu_template.h"
|
|
|
|
#define SHIFT 3
|
|
#include "softmmu_template.h"
|
|
|
|
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
|
|
{
|
|
env->CP0_BadVAddr = addr;
|
|
do_restore_state (retaddr);
|
|
do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
|
}
|
|
|
|
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
|
|
{
|
|
TranslationBlock *tb;
|
|
CPUState *saved_env;
|
|
unsigned long pc;
|
|
int ret;
|
|
|
|
/* XXX: hack to restore env in all cases, even if not called from
|
|
generated code */
|
|
saved_env = env;
|
|
env = cpu_single_env;
|
|
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
|
if (ret) {
|
|
if (retaddr) {
|
|
/* now we have a real cpu fault */
|
|
pc = (unsigned long)retaddr;
|
|
tb = tb_find_pc(pc);
|
|
if (tb) {
|
|
/* the PC is inside the translated code. It means that we have
|
|
a virtual CPU fault */
|
|
cpu_restore_state(tb, env, pc, NULL);
|
|
}
|
|
}
|
|
do_raise_exception_err(env->exception_index, env->error_code);
|
|
}
|
|
env = saved_env;
|
|
}
|
|
|
|
#endif
|