Philippe Mathieu-Daudé ba7b6f025b target/mips: Fix Loongson-3A4000 MSAIR config register ... When using the Loongson-3A4000 CPU, the MSAIR is returned with a zero value (because unimplemented). Checking on real hardware, this value appears incorrect: $ cat /proc/cpuinfo system type : generic-loongson-machine machine : loongson,generic cpu model : Loongson-3 V0.4 FPU V0.1 model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2 ... Checking the CFCMSA opcode result with gdb we get 0x60140: Breakpoint 1, 0x00000001200037c4 in main () 1: x/i $pc => 0x1200037c4 <main+52>: cfcmsa v0,msa_ir (gdb) si 0x00000001200037c8 in main () (gdb) i r v0 v0: 0x60140 MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12, so mask them out, and set MSAIR=0x0140 for the Loongson-3A4000 CPU model added in commit af868995e1. Cc: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211026180920.1085516-1-f4bug@amsat.org>		2021-11-02 14:32:32 +01:00
..
sysemu
tcg	target/mips: Remove one MSA unnecessary decodetree overlap group	2021-11-02 14:32:32 +01:00
cpu-defs.c.inc	target/mips: Fix Loongson-3A4000 MSAIR config register	2021-11-02 14:32:32 +01:00
cpu-param.h
cpu-qom.h	target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed	2021-05-26 15:33:59 -07:00
cpu.c	target/mips: Restrict cpu_exec_interrupt() handler to sysemu	2021-09-14 12:00:21 -07:00
cpu.h	include/exec: Move cpu_signal_handler declaration	2021-09-21 19:36:44 -07:00
fpu_helper.h
fpu.c
gdbstub.c
helper.h	target/mips: Extract NEC Vr54xx helper definitions	2021-08-25 13:02:14 +02:00
internal.h	include/exec: Move cpu_signal_handler declaration	2021-09-21 19:36:44 -07:00
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
kvm_mips.h
kvm.c
meson.build
mips-defs.h
msa.c
TODO