ba62cc56e8
Implement the MVE VMULH insn, which performs a vector multiply and returns the high half of the result. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-14-peter.maydell@linaro.org
391 lines
14 KiB
C
391 lines
14 KiB
C
/*
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* M-profile MVE Operations
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*
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* Copyright (c) 2021 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internals.h"
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#include "vec_internal.h"
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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#include "exec/exec-all.h"
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#include "tcg/tcg.h"
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static uint16_t mve_element_mask(CPUARMState *env)
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{
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/*
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* Return the mask of which elements in the MVE vector should be
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* updated. This is a combination of multiple things:
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* (1) by default, we update every lane in the vector
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* (2) VPT predication stores its state in the VPR register;
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* (3) low-overhead-branch tail predication will mask out part
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* the vector on the final iteration of the loop
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* (4) if EPSR.ECI is set then we must execute only some beats
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* of the insn
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* We combine all these into a 16-bit result with the same semantics
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* as VPR.P0: 0 to mask the lane, 1 if it is active.
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* 8-bit vector ops will look at all bits of the result;
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* 16-bit ops will look at bits 0, 2, 4, ...;
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* 32-bit ops will look at bits 0, 4, 8 and 12.
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* Compare pseudocode GetCurInstrBeat(), though that only returns
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* the 4-bit slice of the mask corresponding to a single beat.
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*/
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uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0);
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if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) {
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mask |= 0xff;
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}
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if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) {
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mask |= 0xff00;
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}
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if (env->v7m.ltpsize < 4 &&
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env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) {
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/*
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* Tail predication active, and this is the last loop iteration.
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* The element size is (1 << ltpsize), and we only want to process
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* loopcount elements, so we want to retain the least significant
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* (loopcount * esize) predicate bits and zero out bits above that.
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*/
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int masklen = env->regs[14] << env->v7m.ltpsize;
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assert(masklen <= 16);
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mask &= MAKE_64BIT_MASK(0, masklen);
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}
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if ((env->condexec_bits & 0xf) == 0) {
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/*
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* ECI bits indicate which beats are already executed;
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* we handle this by effectively predicating them out.
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*/
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int eci = env->condexec_bits >> 4;
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switch (eci) {
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case ECI_NONE:
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break;
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case ECI_A0:
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mask &= 0xfff0;
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break;
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case ECI_A0A1:
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mask &= 0xff00;
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break;
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case ECI_A0A1A2:
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case ECI_A0A1A2B0:
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mask &= 0xf000;
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break;
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default:
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g_assert_not_reached();
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}
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}
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return mask;
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}
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static void mve_advance_vpt(CPUARMState *env)
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{
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/* Advance the VPT and ECI state if necessary */
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uint32_t vpr = env->v7m.vpr;
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unsigned mask01, mask23;
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if ((env->condexec_bits & 0xf) == 0) {
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env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ?
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(ECI_A0 << 4) : (ECI_NONE << 4);
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}
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if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) {
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/* VPT not enabled, nothing to do */
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return;
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}
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mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01);
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mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23);
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if (mask01 > 8) {
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/* high bit set, but not 0b1000: invert the relevant half of P0 */
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vpr ^= 0xff;
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}
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if (mask23 > 8) {
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/* high bit set, but not 0b1000: invert the relevant half of P0 */
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vpr ^= 0xff00;
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}
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vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1);
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vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1);
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env->v7m.vpr = vpr;
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}
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#define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \
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void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \
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{ \
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TYPE *d = vd; \
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uint16_t mask = mve_element_mask(env); \
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unsigned b, e; \
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/* \
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* R_SXTM allows the dest reg to become UNKNOWN for abandoned \
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* beats so we don't care if we update part of the dest and \
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* then take an exception. \
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*/ \
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for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \
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if (mask & (1 << b)) { \
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d[H##ESIZE(e)] = cpu_##LDTYPE##_data_ra(env, addr, GETPC()); \
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} \
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addr += MSIZE; \
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} \
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mve_advance_vpt(env); \
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}
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#define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \
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void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \
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{ \
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TYPE *d = vd; \
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uint16_t mask = mve_element_mask(env); \
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unsigned b, e; \
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for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \
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if (mask & (1 << b)) { \
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cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \
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} \
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addr += MSIZE; \
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} \
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mve_advance_vpt(env); \
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}
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DO_VLDR(vldrb, 1, ldub, 1, uint8_t)
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DO_VLDR(vldrh, 2, lduw, 2, uint16_t)
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DO_VLDR(vldrw, 4, ldl, 4, uint32_t)
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DO_VSTR(vstrb, 1, stb, 1, uint8_t)
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DO_VSTR(vstrh, 2, stw, 2, uint16_t)
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DO_VSTR(vstrw, 4, stl, 4, uint32_t)
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DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t)
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DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t)
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DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t)
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DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t)
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DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t)
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DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t)
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DO_VSTR(vstrb_h, 1, stb, 2, int16_t)
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DO_VSTR(vstrb_w, 1, stb, 4, int32_t)
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DO_VSTR(vstrh_w, 2, stw, 4, int32_t)
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#undef DO_VLDR
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#undef DO_VSTR
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/*
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* The mergemask(D, R, M) macro performs the operation "*D = R" but
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* storing only the bytes which correspond to 1 bits in M,
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* leaving other bytes in *D unchanged. We use _Generic
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* to select the correct implementation based on the type of D.
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*/
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static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask)
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{
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if (mask & 1) {
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*d = r;
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}
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}
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static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask)
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{
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mergemask_ub((uint8_t *)d, r, mask);
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}
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static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask)
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{
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uint16_t bmask = expand_pred_b_data[mask & 3];
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*d = (*d & ~bmask) | (r & bmask);
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}
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static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask)
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{
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mergemask_uh((uint16_t *)d, r, mask);
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}
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static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask)
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{
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uint32_t bmask = expand_pred_b_data[mask & 0xf];
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*d = (*d & ~bmask) | (r & bmask);
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}
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static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask)
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{
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mergemask_uw((uint32_t *)d, r, mask);
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}
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static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask)
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{
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uint64_t bmask = expand_pred_b_data[mask & 0xff];
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*d = (*d & ~bmask) | (r & bmask);
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}
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static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask)
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{
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mergemask_uq((uint64_t *)d, r, mask);
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}
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#define mergemask(D, R, M) \
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_Generic(D, \
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uint8_t *: mergemask_ub, \
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int8_t *: mergemask_sb, \
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uint16_t *: mergemask_uh, \
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int16_t *: mergemask_sh, \
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uint32_t *: mergemask_uw, \
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int32_t *: mergemask_sw, \
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uint64_t *: mergemask_uq, \
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int64_t *: mergemask_sq)(D, R, M)
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void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val)
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{
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/*
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* The generated code already replicated an 8 or 16 bit constant
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* into the 32-bit value, so we only need to write the 32-bit
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* value to all elements of the Qreg, allowing for predication.
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*/
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uint32_t *d = vd;
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uint16_t mask = mve_element_mask(env);
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unsigned e;
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for (e = 0; e < 16 / 4; e++, mask >>= 4) {
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mergemask(&d[H4(e)], val, mask);
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}
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mve_advance_vpt(env);
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}
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#define DO_1OP(OP, ESIZE, TYPE, FN) \
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void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
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{ \
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TYPE *d = vd, *m = vm; \
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uint16_t mask = mve_element_mask(env); \
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unsigned e; \
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for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
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mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \
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} \
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mve_advance_vpt(env); \
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}
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#define DO_CLS_B(N) (clrsb32(N) - 24)
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#define DO_CLS_H(N) (clrsb32(N) - 16)
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DO_1OP(vclsb, 1, int8_t, DO_CLS_B)
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DO_1OP(vclsh, 2, int16_t, DO_CLS_H)
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DO_1OP(vclsw, 4, int32_t, clrsb32)
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#define DO_CLZ_B(N) (clz32(N) - 24)
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#define DO_CLZ_H(N) (clz32(N) - 16)
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DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B)
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DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H)
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DO_1OP(vclzw, 4, uint32_t, clz32)
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DO_1OP(vrev16b, 2, uint16_t, bswap16)
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DO_1OP(vrev32b, 4, uint32_t, bswap32)
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DO_1OP(vrev32h, 4, uint32_t, hswap32)
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DO_1OP(vrev64b, 8, uint64_t, bswap64)
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DO_1OP(vrev64h, 8, uint64_t, hswap64)
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DO_1OP(vrev64w, 8, uint64_t, wswap64)
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#define DO_NOT(N) (~(N))
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DO_1OP(vmvn, 8, uint64_t, DO_NOT)
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#define DO_ABS(N) ((N) < 0 ? -(N) : (N))
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#define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff))
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#define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff))
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DO_1OP(vabsb, 1, int8_t, DO_ABS)
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DO_1OP(vabsh, 2, int16_t, DO_ABS)
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DO_1OP(vabsw, 4, int32_t, DO_ABS)
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/* We can do these 64 bits at a time */
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DO_1OP(vfabsh, 8, uint64_t, DO_FABSH)
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DO_1OP(vfabss, 8, uint64_t, DO_FABSS)
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#define DO_NEG(N) (-(N))
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#define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000))
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#define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000))
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DO_1OP(vnegb, 1, int8_t, DO_NEG)
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DO_1OP(vnegh, 2, int16_t, DO_NEG)
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DO_1OP(vnegw, 4, int32_t, DO_NEG)
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/* We can do these 64 bits at a time */
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DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
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DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
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#define DO_2OP(OP, ESIZE, TYPE, FN) \
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void HELPER(glue(mve_, OP))(CPUARMState *env, \
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void *vd, void *vn, void *vm) \
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{ \
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TYPE *d = vd, *n = vn, *m = vm; \
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uint16_t mask = mve_element_mask(env); \
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unsigned e; \
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for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
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mergemask(&d[H##ESIZE(e)], \
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FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \
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} \
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mve_advance_vpt(env); \
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}
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/* provide unsigned 2-op helpers for all sizes */
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#define DO_2OP_U(OP, FN) \
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DO_2OP(OP##b, 1, uint8_t, FN) \
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DO_2OP(OP##h, 2, uint16_t, FN) \
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DO_2OP(OP##w, 4, uint32_t, FN)
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#define DO_AND(N, M) ((N) & (M))
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#define DO_BIC(N, M) ((N) & ~(M))
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#define DO_ORR(N, M) ((N) | (M))
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#define DO_ORN(N, M) ((N) | ~(M))
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#define DO_EOR(N, M) ((N) ^ (M))
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DO_2OP(vand, 8, uint64_t, DO_AND)
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DO_2OP(vbic, 8, uint64_t, DO_BIC)
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DO_2OP(vorr, 8, uint64_t, DO_ORR)
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DO_2OP(vorn, 8, uint64_t, DO_ORN)
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DO_2OP(veor, 8, uint64_t, DO_EOR)
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#define DO_ADD(N, M) ((N) + (M))
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#define DO_SUB(N, M) ((N) - (M))
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#define DO_MUL(N, M) ((N) * (M))
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DO_2OP_U(vadd, DO_ADD)
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DO_2OP_U(vsub, DO_SUB)
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DO_2OP_U(vmul, DO_MUL)
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/*
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* Because the computation type is at least twice as large as required,
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* these work for both signed and unsigned source types.
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*/
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static inline uint8_t do_mulh_b(int32_t n, int32_t m)
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{
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return (n * m) >> 8;
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}
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static inline uint16_t do_mulh_h(int32_t n, int32_t m)
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{
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return (n * m) >> 16;
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}
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static inline uint32_t do_mulh_w(int64_t n, int64_t m)
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{
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return (n * m) >> 32;
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}
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DO_2OP(vmulhsb, 1, int8_t, do_mulh_b)
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DO_2OP(vmulhsh, 2, int16_t, do_mulh_h)
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DO_2OP(vmulhsw, 4, int32_t, do_mulh_w)
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DO_2OP(vmulhub, 1, uint8_t, do_mulh_b)
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DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h)
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DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w)
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