qemu/target at ba1a6723f58640ba281bc952abc255e97c70bad5 - qemu

History

Richard Henderson f200ff158d Speed empty timer list in qemu_clock_deadline_ns_all.

Implement remainder for Power3.1 hosts.
 Optimize ppc host icache flushing.
 Cleanups to tcg_accel_ops_init.
 Fix mmio crash accessing unmapped physical memory.
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Merge tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/qemu into staging

Speed empty timer list in qemu_clock_deadline_ns_all.
Implement remainder for Power3.1 hosts.
Optimize ppc host icache flushing.
Cleanups to tcg_accel_ops_init.
Fix mmio crash accessing unmapped physical memory.

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# gpg: Signature made Tue 21 Jun 2022 01:45:31 PM PDT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/qemu:
  util/cacheflush: Optimize flushing when ppc host has coherent icache
  util/cacheflush: Merge aarch64 ctr_el0 usage
  util: Merge cacheflush.c and cacheinfo.c
  softmmu: Always initialize xlat in address_space_translate_for_iotlb
  qemu-timer: Skip empty timer lists before locking in qemu_clock_deadline_ns_all
  accel/tcg: Reorganize tcg_accel_ops_init()
  accel/tcg: Init TCG cflags in vCPU thread handler
  target/avr: Drop avr_cpu_memory_rw_debug()
  tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

2022-06-21 13:47:20 -07:00

alpha

…

arm

target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]

2022-06-10 14:32:35 +01:00

avr

target/avr: Drop avr_cpu_memory_rw_debug()

2022-06-20 13:11:36 -07:00

cris

…

hexagon