dcc99bd833
Since commit 12b6e9b27d ("disas: Clean up CPUDebug initialization")
the disassemble_info->bfd_endian enum is set for all targets in
target_disas(). We can directly call print_insn_nios2() and simplify.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210807110939.95853-3-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
515 lines
19 KiB
C
515 lines
19 KiB
C
/* Interface between the opcode library and its callers.
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Written by Cygnus Support, 1993.
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The opcode library (libopcodes.a) provides instruction decoders for
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a large variety of instruction sets, callable with an identical
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interface, for making instruction-processing programs more independent
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of the instruction set being processed. */
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#ifndef DISAS_DIS_ASM_H
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#define DISAS_DIS_ASM_H
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#include "qemu/bswap.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef void *PTR;
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typedef uint64_t bfd_vma;
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typedef int64_t bfd_signed_vma;
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typedef uint8_t bfd_byte;
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#define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)
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#define snprintf_vma(s,ss,x) snprintf (s, ss, "%0" PRIx64, x)
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#define BFD64
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enum bfd_flavour {
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bfd_target_unknown_flavour,
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bfd_target_aout_flavour,
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bfd_target_coff_flavour,
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bfd_target_ecoff_flavour,
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bfd_target_elf_flavour,
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bfd_target_ieee_flavour,
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bfd_target_nlm_flavour,
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bfd_target_oasys_flavour,
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bfd_target_tekhex_flavour,
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bfd_target_srec_flavour,
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bfd_target_ihex_flavour,
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bfd_target_som_flavour,
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bfd_target_os9k_flavour,
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bfd_target_versados_flavour,
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bfd_target_msdos_flavour,
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bfd_target_evax_flavour
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};
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enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
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enum bfd_architecture
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{
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bfd_arch_unknown, /* File arch not known */
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bfd_arch_obscure, /* Arch known, not one of these */
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bfd_arch_m68k, /* Motorola 68xxx */
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#define bfd_mach_m68000 1
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#define bfd_mach_m68008 2
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#define bfd_mach_m68010 3
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#define bfd_mach_m68020 4
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#define bfd_mach_m68030 5
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#define bfd_mach_m68040 6
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#define bfd_mach_m68060 7
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#define bfd_mach_cpu32 8
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#define bfd_mach_mcf5200 9
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#define bfd_mach_mcf5206e 10
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#define bfd_mach_mcf5307 11
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#define bfd_mach_mcf5407 12
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#define bfd_mach_mcf528x 13
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#define bfd_mach_mcfv4e 14
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#define bfd_mach_mcf521x 15
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#define bfd_mach_mcf5249 16
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#define bfd_mach_mcf547x 17
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#define bfd_mach_mcf548x 18
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bfd_arch_vax, /* DEC Vax */
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bfd_arch_i960, /* Intel 960 */
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/* The order of the following is important.
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lower number indicates a machine type that
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only accepts a subset of the instructions
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available to machines with higher numbers.
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The exception is the "ca", which is
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incompatible with all other machines except
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"core". */
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#define bfd_mach_i960_core 1
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#define bfd_mach_i960_ka_sa 2
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#define bfd_mach_i960_kb_sb 3
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#define bfd_mach_i960_mc 4
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#define bfd_mach_i960_xa 5
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#define bfd_mach_i960_ca 6
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#define bfd_mach_i960_jx 7
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#define bfd_mach_i960_hx 8
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bfd_arch_a29k, /* AMD 29000 */
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bfd_arch_sparc, /* SPARC */
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#define bfd_mach_sparc 1
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/* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
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#define bfd_mach_sparc_sparclet 2
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#define bfd_mach_sparc_sparclite 3
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#define bfd_mach_sparc_v8plus 4
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#define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */
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#define bfd_mach_sparc_sparclite_le 6
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#define bfd_mach_sparc_v9 7
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#define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
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#define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
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#define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
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/* Nonzero if MACH has the v9 instruction set. */
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#define bfd_mach_sparc_v9_p(mach) \
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((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
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&& (mach) != bfd_mach_sparc_sparclite_le)
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bfd_arch_mips, /* MIPS Rxxxx */
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#define bfd_mach_mips3000 3000
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#define bfd_mach_mips3900 3900
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#define bfd_mach_mips4000 4000
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#define bfd_mach_mips4010 4010
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#define bfd_mach_mips4100 4100
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#define bfd_mach_mips4300 4300
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#define bfd_mach_mips4400 4400
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#define bfd_mach_mips4600 4600
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#define bfd_mach_mips4650 4650
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#define bfd_mach_mips5000 5000
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#define bfd_mach_mips6000 6000
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#define bfd_mach_mips8000 8000
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#define bfd_mach_mips10000 10000
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#define bfd_mach_mips16 16
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bfd_arch_i386, /* Intel 386 */
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#define bfd_mach_i386_i386 0
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#define bfd_mach_i386_i8086 1
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#define bfd_mach_i386_i386_intel_syntax 2
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#define bfd_mach_x86_64 3
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#define bfd_mach_x86_64_intel_syntax 4
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bfd_arch_we32k, /* AT&T WE32xxx */
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bfd_arch_tahoe, /* CCI/Harris Tahoe */
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bfd_arch_i860, /* Intel 860 */
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bfd_arch_romp, /* IBM ROMP PC/RT */
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bfd_arch_alliant, /* Alliant */
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bfd_arch_convex, /* Convex */
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bfd_arch_m88k, /* Motorola 88xxx */
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bfd_arch_pyramid, /* Pyramid Technology */
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bfd_arch_h8300, /* Hitachi H8/300 */
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#define bfd_mach_h8300 1
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#define bfd_mach_h8300h 2
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#define bfd_mach_h8300s 3
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bfd_arch_powerpc, /* PowerPC */
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#define bfd_mach_ppc 0
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#define bfd_mach_ppc64 1
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#define bfd_mach_ppc_403 403
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#define bfd_mach_ppc_403gc 4030
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#define bfd_mach_ppc_e500 500
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#define bfd_mach_ppc_505 505
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#define bfd_mach_ppc_601 601
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#define bfd_mach_ppc_602 602
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#define bfd_mach_ppc_603 603
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#define bfd_mach_ppc_ec603e 6031
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#define bfd_mach_ppc_604 604
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#define bfd_mach_ppc_620 620
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#define bfd_mach_ppc_630 630
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#define bfd_mach_ppc_750 750
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#define bfd_mach_ppc_860 860
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#define bfd_mach_ppc_a35 35
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#define bfd_mach_ppc_rs64ii 642
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#define bfd_mach_ppc_rs64iii 643
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#define bfd_mach_ppc_7400 7400
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bfd_arch_rs6000, /* IBM RS/6000 */
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bfd_arch_hppa, /* HP PA RISC */
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#define bfd_mach_hppa10 10
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#define bfd_mach_hppa11 11
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#define bfd_mach_hppa20 20
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#define bfd_mach_hppa20w 25
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bfd_arch_d10v, /* Mitsubishi D10V */
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bfd_arch_z8k, /* Zilog Z8000 */
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#define bfd_mach_z8001 1
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#define bfd_mach_z8002 2
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bfd_arch_h8500, /* Hitachi H8/500 */
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bfd_arch_sh, /* Hitachi SH */
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#define bfd_mach_sh 1
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#define bfd_mach_sh2 0x20
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#define bfd_mach_sh_dsp 0x2d
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#define bfd_mach_sh2a 0x2a
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#define bfd_mach_sh2a_nofpu 0x2b
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#define bfd_mach_sh2e 0x2e
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#define bfd_mach_sh3 0x30
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#define bfd_mach_sh3_nommu 0x31
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#define bfd_mach_sh3_dsp 0x3d
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#define bfd_mach_sh3e 0x3e
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#define bfd_mach_sh4 0x40
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#define bfd_mach_sh4_nofpu 0x41
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#define bfd_mach_sh4_nommu_nofpu 0x42
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#define bfd_mach_sh4a 0x4a
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#define bfd_mach_sh4a_nofpu 0x4b
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#define bfd_mach_sh4al_dsp 0x4d
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#define bfd_mach_sh5 0x50
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bfd_arch_alpha, /* Dec Alpha */
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#define bfd_mach_alpha 1
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#define bfd_mach_alpha_ev4 0x10
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#define bfd_mach_alpha_ev5 0x20
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#define bfd_mach_alpha_ev6 0x30
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bfd_arch_arm, /* Advanced Risc Machines ARM */
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#define bfd_mach_arm_unknown 0
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#define bfd_mach_arm_2 1
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#define bfd_mach_arm_2a 2
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#define bfd_mach_arm_3 3
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#define bfd_mach_arm_3M 4
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#define bfd_mach_arm_4 5
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#define bfd_mach_arm_4T 6
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#define bfd_mach_arm_5 7
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#define bfd_mach_arm_5T 8
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#define bfd_mach_arm_5TE 9
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#define bfd_mach_arm_XScale 10
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#define bfd_mach_arm_ep9312 11
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#define bfd_mach_arm_iWMMXt 12
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#define bfd_mach_arm_iWMMXt2 13
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bfd_arch_ns32k, /* National Semiconductors ns32000 */
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bfd_arch_w65, /* WDC 65816 */
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bfd_arch_tic30, /* Texas Instruments TMS320C30 */
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bfd_arch_v850, /* NEC V850 */
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#define bfd_mach_v850 0
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bfd_arch_arc, /* Argonaut RISC Core */
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#define bfd_mach_arc_base 0
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bfd_arch_m32r, /* Mitsubishi M32R/D */
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#define bfd_mach_m32r 0 /* backwards compatibility */
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bfd_arch_mn10200, /* Matsushita MN10200 */
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bfd_arch_mn10300, /* Matsushita MN10300 */
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bfd_arch_avr, /* AVR microcontrollers */
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#define bfd_mach_avr1 1
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#define bfd_mach_avr2 2
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#define bfd_mach_avr25 25
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#define bfd_mach_avr3 3
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#define bfd_mach_avr31 31
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#define bfd_mach_avr35 35
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#define bfd_mach_avr4 4
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#define bfd_mach_avr5 5
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#define bfd_mach_avr51 51
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#define bfd_mach_avr6 6
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#define bfd_mach_avrtiny 100
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#define bfd_mach_avrxmega1 101
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#define bfd_mach_avrxmega2 102
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#define bfd_mach_avrxmega3 103
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#define bfd_mach_avrxmega4 104
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#define bfd_mach_avrxmega5 105
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#define bfd_mach_avrxmega6 106
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#define bfd_mach_avrxmega7 107
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bfd_arch_cris, /* Axis CRIS */
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#define bfd_mach_cris_v0_v10 255
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#define bfd_mach_cris_v32 32
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#define bfd_mach_cris_v10_v32 1032
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bfd_arch_microblaze, /* Xilinx MicroBlaze. */
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bfd_arch_moxie, /* The Moxie core. */
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bfd_arch_ia64, /* HP/Intel ia64 */
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#define bfd_mach_ia64_elf64 64
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#define bfd_mach_ia64_elf32 32
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bfd_arch_nios2, /* Nios II */
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#define bfd_mach_nios2 0
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#define bfd_mach_nios2r1 1
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#define bfd_mach_nios2r2 2
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bfd_arch_rx, /* Renesas RX */
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#define bfd_mach_rx 0x75
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#define bfd_mach_rx_v2 0x76
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#define bfd_mach_rx_v3 0x77
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bfd_arch_last
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};
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#define bfd_mach_s390_31 31
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#define bfd_mach_s390_64 64
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typedef struct symbol_cache_entry
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{
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const char *name;
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union
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{
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PTR p;
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bfd_vma i;
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} udata;
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} asymbol;
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typedef int (*fprintf_function)(FILE *f, const char *fmt, ...)
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GCC_FMT_ATTR(2, 3);
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enum dis_insn_type {
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dis_noninsn, /* Not a valid instruction */
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dis_nonbranch, /* Not a branch instruction */
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dis_branch, /* Unconditional branch */
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dis_condbranch, /* Conditional branch */
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dis_jsr, /* Jump to subroutine */
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dis_condjsr, /* Conditional jump to subroutine */
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dis_dref, /* Data reference instruction */
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dis_dref2 /* Two data references in instruction */
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};
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/* This struct is passed into the instruction decoding routine,
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and is passed back out into each callback. The various fields are used
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for conveying information from your main routine into your callbacks,
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for passing information into the instruction decoders (such as the
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addresses of the callback functions), or for passing information
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back from the instruction decoders to their callers.
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It must be initialized before it is first passed; this can be done
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by hand, or using one of the initialization macros below. */
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typedef struct disassemble_info {
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fprintf_function fprintf_func;
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FILE *stream;
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PTR application_data;
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/* Target description. We could replace this with a pointer to the bfd,
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but that would require one. There currently isn't any such requirement
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so to avoid introducing one we record these explicitly. */
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/* The bfd_flavour. This can be bfd_target_unknown_flavour. */
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enum bfd_flavour flavour;
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/* The bfd_arch value. */
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enum bfd_architecture arch;
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/* The bfd_mach value. */
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unsigned long mach;
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/* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
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enum bfd_endian endian;
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/* An array of pointers to symbols either at the location being disassembled
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or at the start of the function being disassembled. The array is sorted
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so that the first symbol is intended to be the one used. The others are
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present for any misc. purposes. This is not set reliably, but if it is
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not NULL, it is correct. */
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asymbol **symbols;
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/* Number of symbols in array. */
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int num_symbols;
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/* For use by the disassembler.
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The top 16 bits are reserved for public use (and are documented here).
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The bottom 16 bits are for the internal use of the disassembler. */
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unsigned long flags;
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#define INSN_HAS_RELOC 0x80000000
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#define INSN_ARM_BE32 0x00010000
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PTR private_data;
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/* Function used to get bytes to disassemble. MEMADDR is the
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address of the stuff to be disassembled, MYADDR is the address to
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put the bytes in, and LENGTH is the number of bytes to read.
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INFO is a pointer to this struct.
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Returns an errno value or 0 for success. */
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int (*read_memory_func)
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(bfd_vma memaddr, bfd_byte *myaddr, int length,
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struct disassemble_info *info);
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/* Function which should be called if we get an error that we can't
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recover from. STATUS is the errno value from read_memory_func and
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MEMADDR is the address that we were trying to read. INFO is a
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pointer to this struct. */
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void (*memory_error_func)
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(int status, bfd_vma memaddr, struct disassemble_info *info);
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/* Function called to print ADDR. */
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void (*print_address_func)
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(bfd_vma addr, struct disassemble_info *info);
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/* Function called to print an instruction. The function is architecture
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* specific.
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*/
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int (*print_insn)(bfd_vma addr, struct disassemble_info *info);
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/* Function called to determine if there is a symbol at the given ADDR.
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If there is, the function returns 1, otherwise it returns 0.
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This is used by ports which support an overlay manager where
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the overlay number is held in the top part of an address. In
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some circumstances we want to include the overlay number in the
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address, (normally because there is a symbol associated with
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that address), but sometimes we want to mask out the overlay bits. */
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int (* symbol_at_address_func)
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(bfd_vma addr, struct disassemble_info * info);
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/* These are for buffer_read_memory. */
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const bfd_byte *buffer;
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bfd_vma buffer_vma;
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int buffer_length;
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/* This variable may be set by the instruction decoder. It suggests
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the number of bytes objdump should display on a single line. If
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the instruction decoder sets this, it should always set it to
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the same value in order to get reasonable looking output. */
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int bytes_per_line;
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/* the next two variables control the way objdump displays the raw data */
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/* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
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/* output will look like this:
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00: 00000000 00000000
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with the chunks displayed according to "display_endian". */
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int bytes_per_chunk;
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enum bfd_endian display_endian;
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/* Results from instruction decoders. Not all decoders yet support
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this information. This info is set each time an instruction is
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decoded, and is only valid for the last such instruction.
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To determine whether this decoder supports this information, set
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insn_info_valid to 0, decode an instruction, then check it. */
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char insn_info_valid; /* Branch info has been set. */
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char branch_delay_insns; /* How many sequential insn's will run before
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a branch takes effect. (0 = normal) */
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char data_size; /* Size of data reference in insn, in bytes */
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enum dis_insn_type insn_type; /* Type of instruction */
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bfd_vma target; /* Target address of branch or dref, if known;
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zero if unknown. */
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bfd_vma target2; /* Second target address for dref2 */
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/* Command line options specific to the target disassembler. */
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char * disassembler_options;
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/* Field intended to be used by targets in any way they deem suitable. */
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int64_t target_info;
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/* Options for Capstone disassembly. */
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int cap_arch;
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int cap_mode;
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int cap_insn_unit;
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int cap_insn_split;
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} disassemble_info;
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/* Standard disassemblers. Disassemble one instruction at the given
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target address. Return number of bytes processed. */
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typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
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int print_insn_tci(bfd_vma, disassemble_info*);
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int print_insn_big_mips (bfd_vma, disassemble_info*);
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int print_insn_little_mips (bfd_vma, disassemble_info*);
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int print_insn_nanomips (bfd_vma, disassemble_info*);
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int print_insn_i386 (bfd_vma, disassemble_info*);
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int print_insn_m68k (bfd_vma, disassemble_info*);
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int print_insn_z8001 (bfd_vma, disassemble_info*);
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int print_insn_z8002 (bfd_vma, disassemble_info*);
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int print_insn_h8300 (bfd_vma, disassemble_info*);
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int print_insn_h8300h (bfd_vma, disassemble_info*);
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int print_insn_h8300s (bfd_vma, disassemble_info*);
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int print_insn_h8500 (bfd_vma, disassemble_info*);
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int print_insn_arm_a64 (bfd_vma, disassemble_info*);
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int print_insn_alpha (bfd_vma, disassemble_info*);
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disassembler_ftype arc_get_disassembler (int, int);
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int print_insn_arm (bfd_vma, disassemble_info*);
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int print_insn_sparc (bfd_vma, disassemble_info*);
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int print_insn_big_a29k (bfd_vma, disassemble_info*);
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int print_insn_little_a29k (bfd_vma, disassemble_info*);
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int print_insn_i960 (bfd_vma, disassemble_info*);
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int print_insn_sh (bfd_vma, disassemble_info*);
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int print_insn_shl (bfd_vma, disassemble_info*);
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int print_insn_hppa (bfd_vma, disassemble_info*);
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int print_insn_m32r (bfd_vma, disassemble_info*);
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int print_insn_m88k (bfd_vma, disassemble_info*);
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int print_insn_mn10200 (bfd_vma, disassemble_info*);
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int print_insn_mn10300 (bfd_vma, disassemble_info*);
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int print_insn_ns32k (bfd_vma, disassemble_info*);
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int print_insn_big_powerpc (bfd_vma, disassemble_info*);
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int print_insn_little_powerpc (bfd_vma, disassemble_info*);
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int print_insn_rs6000 (bfd_vma, disassemble_info*);
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int print_insn_w65 (bfd_vma, disassemble_info*);
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int print_insn_d10v (bfd_vma, disassemble_info*);
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int print_insn_v850 (bfd_vma, disassemble_info*);
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int print_insn_tic30 (bfd_vma, disassemble_info*);
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int print_insn_ppc (bfd_vma, disassemble_info*);
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int print_insn_s390 (bfd_vma, disassemble_info*);
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int print_insn_crisv32 (bfd_vma, disassemble_info*);
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int print_insn_crisv10 (bfd_vma, disassemble_info*);
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int print_insn_microblaze (bfd_vma, disassemble_info*);
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int print_insn_ia64 (bfd_vma, disassemble_info*);
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int print_insn_nios2(bfd_vma, disassemble_info*);
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int print_insn_xtensa (bfd_vma, disassemble_info*);
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int print_insn_riscv32 (bfd_vma, disassemble_info*);
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int print_insn_riscv64 (bfd_vma, disassemble_info*);
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int print_insn_rx(bfd_vma, disassemble_info *);
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int print_insn_hexagon(bfd_vma, disassemble_info *);
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#ifdef CONFIG_CAPSTONE
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bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size);
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bool cap_disas_host(disassemble_info *info, const void *code, size_t size);
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bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count);
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bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size);
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#else
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# define cap_disas_target(i, p, s) false
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# define cap_disas_host(i, p, s) false
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# define cap_disas_monitor(i, p, c) false
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# define cap_disas_plugin(i, p, c) false
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#endif /* CONFIG_CAPSTONE */
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|
#ifndef ATTRIBUTE_UNUSED
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#define ATTRIBUTE_UNUSED __attribute__((unused))
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#endif
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/* from libbfd */
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static inline bfd_vma bfd_getl64(const bfd_byte *addr)
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|
{
|
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return ldq_le_p(addr);
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|
}
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static inline bfd_vma bfd_getl32(const bfd_byte *addr)
|
|
{
|
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return (uint32_t)ldl_le_p(addr);
|
|
}
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|
|
|
static inline bfd_vma bfd_getl16(const bfd_byte *addr)
|
|
{
|
|
return lduw_le_p(addr);
|
|
}
|
|
|
|
static inline bfd_vma bfd_getb32(const bfd_byte *addr)
|
|
{
|
|
return (uint32_t)ldl_be_p(addr);
|
|
}
|
|
|
|
static inline bfd_vma bfd_getb16(const bfd_byte *addr)
|
|
{
|
|
return lduw_be_p(addr);
|
|
}
|
|
|
|
typedef bool bfd_boolean;
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* DISAS_DIS_ASM_H */
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