9877ea05de
Like cpu_in_exclusive_context, but also true if there is no other cpu against which we could race. Use it in tb_flush as a direct replacement. Use it in cpu_loop_exit_atomic to ensure that there is no loop against cpu_exec_step_atomic. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
82 lines
2.4 KiB
C
82 lines
2.4 KiB
C
/*
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* Internal execution defines for qemu
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef ACCEL_TCG_INTERNAL_H
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#define ACCEL_TCG_INTERNAL_H
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#include "exec/exec-all.h"
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/*
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* Access to the various translations structures need to be serialised
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* via locks for consistency. In user-mode emulation access to the
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* memory related structures are protected with mmap_lock.
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* In !user-mode we use per-page locks.
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*/
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#ifdef CONFIG_SOFTMMU
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#define assert_memory_lock()
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#else
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#define assert_memory_lock() tcg_debug_assert(have_mmap_lock())
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#endif
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#if defined(CONFIG_SOFTMMU) && defined(CONFIG_DEBUG_TCG)
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void assert_no_pages_locked(void);
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#else
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static inline void assert_no_pages_locked(void) { }
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#endif
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#ifdef CONFIG_USER_ONLY
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static inline void page_table_config_init(void) { }
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#else
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void page_table_config_init(void);
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#endif
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#ifdef CONFIG_SOFTMMU
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void tb_invalidate_phys_range_fast(ram_addr_t ram_addr,
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unsigned size,
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uintptr_t retaddr);
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G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
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#endif /* CONFIG_SOFTMMU */
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TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc,
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target_ulong cs_base, uint32_t flags,
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int cflags);
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void page_init(void);
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void tb_htable_init(void);
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void tb_reset_jump(TranslationBlock *tb, int n);
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TranslationBlock *tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
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tb_page_addr_t phys_page2);
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bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc);
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void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
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uintptr_t host_pc);
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/* Return the current PC from CPU, which may be cached in TB. */
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static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb)
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{
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if (tb_cflags(tb) & CF_PCREL) {
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return cpu->cc->get_pc(cpu);
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} else {
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return tb->pc;
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}
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}
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/*
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* Return true if CS is not running in parallel with other cpus, either
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* because there are no other cpus or we are within an exclusive context.
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*/
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static inline bool cpu_in_serial_context(CPUState *cs)
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{
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return !(cs->tcg_cflags & CF_PARALLEL) || cpu_in_exclusive_context(cs);
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}
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extern int64_t max_delay;
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extern int64_t max_advance;
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extern bool one_insn_per_tb;
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#endif /* ACCEL_TCG_INTERNAL_H */
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