0694dabe97
This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/*
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* QEMU model of the SiFive SPI Controller
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*
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* Copyright (c) 2021 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_SPI_H
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#define HW_SIFIVE_SPI_H
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#define SIFIVE_SPI_REG_NUM (0x78 / 4)
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#define TYPE_SIFIVE_SPI "sifive.spi"
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#define SIFIVE_SPI(obj) OBJECT_CHECK(SiFiveSPIState, (obj), TYPE_SIFIVE_SPI)
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typedef struct SiFiveSPIState {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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qemu_irq irq;
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uint32_t num_cs;
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qemu_irq *cs_lines;
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SSIBus *spi;
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Fifo8 tx_fifo;
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Fifo8 rx_fifo;
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uint32_t regs[SIFIVE_SPI_REG_NUM];
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} SiFiveSPIState;
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#endif /* HW_SIFIVE_SPI_H */
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