qemu/include/hw/riscv/spike.h
Alistair Francis 26cd0362dd hw/riscv: spike: Remove deprecated ISA specific machines
The ISA specific Spike machines have been deprecated in QEMU since 4.1,
let's finally remove them.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2020-06-03 09:11:51 -07:00

48 lines
1.1 KiB
C

/*
* Spike machine interface
*
* Copyright (c) 2017 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_RISCV_SPIKE_H
#define HW_RISCV_SPIKE_H
#include "hw/riscv/riscv_hart.h"
#include "hw/sysbus.h"
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
RISCVHartArrayState soc;
void *fdt;
int fdt_size;
} SpikeState;
enum {
SPIKE_MROM,
SPIKE_CLINT,
SPIKE_DRAM
};
#if defined(TARGET_RISCV32)
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
#endif
#endif