0e2a3ec368
Until v2.07s, the VRMA page size (L||LP) was encoded in LPCR[VRMASD].
In v3.0 that moved to the partition table PS field.
The powernv machine can now run KVM HPT guests on POWER9/10 CPUs with
this fix and the patch to add ASDR.
Fixes: 3367c62f52 ("target/ppc: Support for POWER9 native hash")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230730111842.39292-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
181 lines
6.5 KiB
C
181 lines
6.5 KiB
C
#ifndef MMU_HASH64_H
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#define MMU_HASH64_H
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#ifndef CONFIG_USER_ONLY
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#ifdef TARGET_PPC64
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void dump_slb(PowerPCCPU *cpu);
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int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
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target_ulong esid, target_ulong vsid);
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bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
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bool guest_visible);
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void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
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target_ulong pte_index,
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target_ulong pte0, target_ulong pte1);
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unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
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uint64_t pte0, uint64_t pte1);
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void ppc_hash64_init(PowerPCCPU *cpu);
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void ppc_hash64_finalize(PowerPCCPU *cpu);
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#endif
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/*
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* SLB definitions
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*/
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/* Bits in the SLB ESID word */
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#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
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#define SLB_ESID_V 0x0000000008000000ULL /* valid */
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/* Bits in the SLB VSID word */
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#define SLB_VSID_SHIFT 12
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#define SLB_VSID_SHIFT_1T 24
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#define SLB_VSID_SSIZE_SHIFT 62
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#define SLB_VSID_B 0xc000000000000000ULL
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#define SLB_VSID_B_256M 0x0000000000000000ULL
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#define SLB_VSID_B_1T 0x4000000000000000ULL
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#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
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#define SLB_VSID_VRMA (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
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#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
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#define SLB_VSID_KS 0x0000000000000800ULL
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#define SLB_VSID_KP 0x0000000000000400ULL
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#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
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#define SLB_VSID_L 0x0000000000000100ULL
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#define SLB_VSID_L_SHIFT PPC_BIT_NR(55)
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#define SLB_VSID_C 0x0000000000000080ULL /* class */
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#define SLB_VSID_LP 0x0000000000000030ULL
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#define SLB_VSID_LP_SHIFT PPC_BIT_NR(59)
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#define SLB_VSID_ATTR 0x0000000000000FFFULL
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#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
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#define SLB_VSID_4K 0x0000000000000000ULL
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#define SLB_VSID_64K 0x0000000000000110ULL
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#define SLB_VSID_16M 0x0000000000000100ULL
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#define SLB_VSID_16G 0x0000000000000120ULL
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/*
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* Hash page table definitions
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*/
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#define SDR_64_HTABORG 0x0FFFFFFFFFFC0000ULL
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#define SDR_64_HTABSIZE 0x000000000000001FULL
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#define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL
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#define PATE0_PS PPC_BITMASK(56, 58)
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#define PATE0_GET_PS(dw0) (((dw0) & PATE0_PS) >> PPC_BIT_NR(58))
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#define HPTES_PER_GROUP 8
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#define HASH_PTE_SIZE_64 16
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#define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
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#define HPTE64_V_SSIZE SLB_VSID_B
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#define HPTE64_V_SSIZE_256M SLB_VSID_B_256M
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#define HPTE64_V_SSIZE_1T SLB_VSID_B_1T
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#define HPTE64_V_SSIZE_SHIFT 62
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#define HPTE64_V_AVPN_SHIFT 7
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#define HPTE64_V_AVPN 0x3fffffffffffff80ULL
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#define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
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#define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
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#define HPTE64_V_BOLTED 0x0000000000000010ULL
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#define HPTE64_V_LARGE 0x0000000000000004ULL
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#define HPTE64_V_SECONDARY 0x0000000000000002ULL
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#define HPTE64_V_VALID 0x0000000000000001ULL
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#define HPTE64_R_PP0 0x8000000000000000ULL
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#define HPTE64_R_TS 0x4000000000000000ULL
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#define HPTE64_R_KEY_HI 0x3000000000000000ULL
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#define HPTE64_R_RPN_SHIFT 12
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#define HPTE64_R_RPN 0x0ffffffffffff000ULL
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#define HPTE64_R_FLAGS 0x00000000000003ffULL
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#define HPTE64_R_PP 0x0000000000000003ULL
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#define HPTE64_R_N 0x0000000000000004ULL
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#define HPTE64_R_G 0x0000000000000008ULL
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#define HPTE64_R_M 0x0000000000000010ULL
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#define HPTE64_R_I 0x0000000000000020ULL
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#define HPTE64_R_W 0x0000000000000040ULL
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#define HPTE64_R_WIMG 0x0000000000000078ULL
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#define HPTE64_R_C 0x0000000000000080ULL
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#define HPTE64_R_R 0x0000000000000100ULL
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#define HPTE64_R_KEY_LO 0x0000000000000e00ULL
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#define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 57) | \
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(((x) & HPTE64_R_KEY_LO) >> 9))
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#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
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#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
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/* PTE offsets */
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#define HPTE64_DW1 (HASH_PTE_SIZE_64 / 2)
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#define HPTE64_DW1_R (HPTE64_DW1 + 6)
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#define HPTE64_DW1_C (HPTE64_DW1 + 7)
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/* Format changes for ARCH v3 */
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#define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL
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#define HPTE64_R_3_0_SSIZE_SHIFT 58
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#define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT)
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struct ppc_hash_pte64 {
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uint64_t pte0, pte1;
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};
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const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
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hwaddr ptex, int n);
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void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
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hwaddr ptex, int n);
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static inline uint64_t ppc_hash64_hpte0(PowerPCCPU *cpu,
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const ppc_hash_pte64_t *hptes, int i)
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{
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return ldq_p(&(hptes[i].pte0));
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}
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static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
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const ppc_hash_pte64_t *hptes, int i)
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{
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return ldq_p(&(hptes[i].pte1));
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}
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/*
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* MMU Options
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*/
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struct PPCHash64PageSize {
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uint32_t page_shift; /* Page shift (or 0) */
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uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
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};
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typedef struct PPCHash64PageSize PPCHash64PageSize;
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struct PPCHash64SegmentPageSizes {
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uint32_t page_shift; /* Base page shift of segment (or 0) */
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uint32_t slb_enc; /* SLB encoding for BookS */
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PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ];
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};
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struct PPCHash64Options {
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#define PPC_HASH64_1TSEG 0x00001
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#define PPC_HASH64_AMR 0x00002
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#define PPC_HASH64_CI_LARGEPAGE 0x00004
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unsigned flags;
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unsigned slb_size;
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PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
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};
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extern const PPCHash64Options ppc_hash64_opts_basic;
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extern const PPCHash64Options ppc_hash64_opts_POWER7;
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static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature)
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{
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return !!(cpu->hash64_opts->flags & feature);
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}
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#endif /* CONFIG_USER_ONLY */
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#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
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static inline void ppc_hash64_init(PowerPCCPU *cpu)
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{
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}
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static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
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{
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}
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#endif
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#endif /* MMU_HASH64_H */
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