Daniel Henrique Barboza b71f9dcada target/riscv/cpu.c: add satp_mode properties earlier ... riscv_cpu_add_user_properties() ended up with an excess of "#ifndef CONFIG_USER_ONLY" blocks after changes that added KVM properties handling. KVM specific properties are required to be created earlier than their TCG counterparts, but the remaining props can be created at any order. Move riscv_add_satp_mode_properties() to the start of the function, inside the !CONFIG_USER_ONLY block already present there, to remove the last ifndef block. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230706101738.460804-16-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-07-10 22:29:20 +10:00
..
insn_trans	target/riscv: Add support for Zvfbfwma extension	2023-07-10 22:29:15 +10:00
arch_dump.c	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	riscv: Make sure an exception is raised if a pte is malformed	2023-05-05 10:49:50 +10:00
cpu_cfg.h	target/riscv: Add properties for BF16 extensions	2023-07-10 22:29:15 +10:00
cpu_helper.c	target/riscv: Set the correct exception for implict G-stage translation fail	2023-07-10 22:29:15 +10:00
cpu_user.h
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
cpu-param.h	target/riscv: Remove NB_MMU_MODES define	2023-03-13 06:44:37 -07:00
cpu-qom.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
cpu.c	target/riscv/cpu.c: add satp_mode properties earlier	2023-07-10 22:29:20 +10:00
cpu.h	target/riscv/cpu: add misa_ext_info_arr[]	2023-07-10 22:29:20 +10:00
crypto_helper.c	target/riscv: Use aesdec_ISB_ISR_IMC_AK	2023-07-09 13:47:17 +01:00
csr.c	target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV	2023-07-10 22:29:14 +10:00
debug.c	target/riscv: Fix lines with over 80 characters	2023-05-05 10:49:50 +10:00
debug.h	target/riscv: Add itrigger support when icount is enabled	2023-01-06 10:42:55 +10:00
fpu_helper.c	target/riscv: Add support for Zfbfmin extension	2023-07-10 22:29:15 +10:00
gdbstub.c	target/riscv: Use PRV_RESERVED instead of PRV_H	2023-05-05 10:49:50 +10:00
helper.h	target/riscv: Add support for Zvfbfwma extension	2023-07-10 22:29:15 +10:00
insn16.decode	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00
insn32.decode	target/riscv: Add support for Zvfbfwma extension	2023-07-10 22:29:15 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: Introduce mmuidx_2stage	2023-05-05 10:49:50 +10:00
Kconfig
kvm_riscv.h	target/riscv: use KVM scratch CPUs to init KVM properties	2023-07-10 22:29:15 +10:00
kvm-stub.c
kvm.c	target/riscv/kvm.c: add multi-letter extension KVM properties	2023-07-10 22:29:20 +10:00
m128_helper.c	target/riscv: Fix format for indentation	2023-05-05 10:49:50 +10:00
machine.c	target/riscv: Restrict KVM-specific fields from ArchCPU	2023-06-28 14:27:59 +02:00
meson.build	meson: Replace softmmu_ss -> system_ss	2023-06-20 10:01:30 +02:00
monitor.c	target/riscv: remove RISCV_FEATURE_MMU	2023-03-01 13:47:15 -08:00
op_helper.c	target/riscv: Make MPV only work when MPP != PRV_M	2023-07-10 22:29:14 +10:00
pmp.c	target/riscv: Smepmp: Return error when access permission not allowed in PMP	2023-06-13 17:45:30 +10:00
pmp.h	target/riscv: Change the return type of pmp_hart_has_privs() to bool	2023-06-13 17:09:13 +10:00
pmu.c	target/riscv: Fix lines with over 80 characters	2023-05-05 10:49:50 +10:00
pmu.h	riscv: Clean up includes	2023-02-08 07:28:05 +01:00
riscv-qmp-cmds.c	target/riscv: add TYPE_RISCV_DYNAMIC_CPU	2023-05-05 10:49:50 +10:00
sbi_ecall_interface.h	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
time_helper.c	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
time_helper.h	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
trace-events
trace.h
translate.c	target/riscv: Add support for Zfbfmin extension	2023-07-10 22:29:15 +10:00
vector_helper.c	target/riscv: Add support for Zvfbfwma extension	2023-07-10 22:29:15 +10:00
xthead.decode	RISC-V: Adding XTheadFmv ISA extension	2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode
zce_helper.c	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00